Oscillatory Associative Memory with Exponential Capacity
Taosha Guo, Arie Ogranovich, Arvind R. Venkatakrishnan, Madelyn R. Shapiro, Francesco Bullo, Fabio Pasqualetti
TL;DR
The paper tackles the memory-capacity bottleneck of classic associative memories by proposing a Kuramoto-oscillator-based architecture on a 1D honeycomb topology. It analytically characterizes the stable phase-locked configurations, deriving explicit phase-difference structures and a winding-number framework that yields no spurious memories. The core result is exponential capacity, with $N_{eq} = \bigl(2 \lceil \tfrac{n_c}{4} \rceil - 1\bigr)^m$ stable memories and $C = p/n$ where $p = N_{eq}$ and $n = m(n_c - 1) + 1$, supported by numerical comparisons to alternative topologies. This work provides theoretical guarantees and practical guidance for energy-efficient, scalable associative memory hardware using oscillator networks.
Abstract
The slowing of Moore's law and the increasing energy demands of machine learning present critical challenges for both the hardware and machine learning communities, and drive the development of novel computing paradigms. Of particular interest is the challenge of incorporating memory efficiently into the learning process. Inspired by how human brains store and retrieve information, associative memory mechanisms provide a class of computational methods that can store and retrieve patterns in a robust, energy-efficient manner. Existing associative memory architectures, such as the celebrated Hopfield model and oscillatory associative memory networks, store patterns as stable equilibria of network dynamics. However, the capacity (i.e. the number of patterns that a network can memorize normalized by their number of nodes) of existing oscillatory models have been shown to decrease with the size of the network, making them impractical for large-scale, real-world applications. In this paper, we propose a novel associative memory architecture based on Kuramoto oscillators. We show that the capacity of our associative memory network increases exponentially with network size and features no spurious memories. In addition, we present algorithms and numerical experiments to support these theoretical findings, providing guidelines for the hardware implementation of the proposed associative memory networks.
