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QUITS: A modular Qldpc code circUIT Simulator

Mingyu Kang, Yingjia Lin, Hanwen Yao, Mert Gökduman, Arianna Meinking, Kenneth R. Brown

TL;DR

QUITS delivers an open-source, modular framework for end-to-end circuit-level simulation of quantum LDPC codes by integrating versatile QLDPC families (HGP, QLP, BPC) with a unified syndrome-extraction circuit and a sliding-window BP-based decoder supplemented by post-processing. The approach enables rigorous assessment of trade-offs between decoding time and logical accuracy under realistic circuit-level noise, revealing thresholds near a few per mille and substantial reductions in syndrome-extraction depth for certain codes. Key findings include evidence of an effective distance reduction at low noise and the importance of circuit-level design choices (window size, inner decoder, and detector modeling) on LFR and runtime. The work establishes QUITS as a practical benchmarking platform to guide code design, circuit synthesis, and decoder development for high-rate QLDPC codes in fault-tolerant quantum computing, with open avenues for extending to logical operations and deeper analyses of decoding failure mechanisms.

Abstract

To achieve quantum fault tolerance with lower overhead, quantum low-density parity-check (QLDPC) codes have emerged as a promising alternative to topological codes such as the surface code, offering higher code rates. To support their study, an end-to-end framework for simulating QLDPC codes at the circuit level is needed. In this work, we present QUITS, a modular and flexible circuit-level simulator for QLDPC codes. Its design allows users to freely combine LDPC code constructions, syndrome extraction circuits, decoding algorithms, and noise models, enabling comprehensive and customizable studies of the performance of QLDPC codes under circuit-level noise. QUITS supports several leading QLDPC families, including hypergraph product codes, lifted product codes, and balanced product codes. As part of the framework, we introduce a syndrome extraction circuit improved from Tremblay, Delfosse, and Beverland [Phys. Rev. Lett. 129, 050504 (2022)] that applies to all three code families. In particular, for a small hypergraph product code, our circuit achieves lower depth than the conventional method, resulting in improved logical performance. Using QUITS, we evaluate the performance of state-of-the-art QLDPC codes and decoders under various settings, revealing trade-offs between the decoding runtime and the logical failure rate. The source code of QUITS is available online.

QUITS: A modular Qldpc code circUIT Simulator

TL;DR

QUITS delivers an open-source, modular framework for end-to-end circuit-level simulation of quantum LDPC codes by integrating versatile QLDPC families (HGP, QLP, BPC) with a unified syndrome-extraction circuit and a sliding-window BP-based decoder supplemented by post-processing. The approach enables rigorous assessment of trade-offs between decoding time and logical accuracy under realistic circuit-level noise, revealing thresholds near a few per mille and substantial reductions in syndrome-extraction depth for certain codes. Key findings include evidence of an effective distance reduction at low noise and the importance of circuit-level design choices (window size, inner decoder, and detector modeling) on LFR and runtime. The work establishes QUITS as a practical benchmarking platform to guide code design, circuit synthesis, and decoder development for high-rate QLDPC codes in fault-tolerant quantum computing, with open avenues for extending to logical operations and deeper analyses of decoding failure mechanisms.

Abstract

To achieve quantum fault tolerance with lower overhead, quantum low-density parity-check (QLDPC) codes have emerged as a promising alternative to topological codes such as the surface code, offering higher code rates. To support their study, an end-to-end framework for simulating QLDPC codes at the circuit level is needed. In this work, we present QUITS, a modular and flexible circuit-level simulator for QLDPC codes. Its design allows users to freely combine LDPC code constructions, syndrome extraction circuits, decoding algorithms, and noise models, enabling comprehensive and customizable studies of the performance of QLDPC codes under circuit-level noise. QUITS supports several leading QLDPC families, including hypergraph product codes, lifted product codes, and balanced product codes. As part of the framework, we introduce a syndrome extraction circuit improved from Tremblay, Delfosse, and Beverland [Phys. Rev. Lett. 129, 050504 (2022)] that applies to all three code families. In particular, for a small hypergraph product code, our circuit achieves lower depth than the conventional method, resulting in improved logical performance. Using QUITS, we evaluate the performance of state-of-the-art QLDPC codes and decoders under various settings, revealing trade-offs between the decoding runtime and the logical failure rate. The source code of QUITS is available online.

Paper Structure

This paper contains 20 sections, 6 equations, 6 figures, 2 tables, 1 algorithm.

Figures (6)

  • Figure 1: Overview of QUITS. QUITS provides a streamlined framework for QLDPC codes simulation. The shaded areas are the modularized functions of QUITS. Given code parameters and an error model as the input, QUITS calls Stim and customized decoders to perform QLDPC simulation and estimates the logical failure rate.
  • Figure 2: QLDPC codes. Filled blue circles, green diamonds, and purple squares represent the data, $Z$-type syndrome, and $X$-type syndrome qubits, respectively. 3-dimensional symbols represent the lifted nodes, each of which contains $l$ qubits of the corresponding type, where $l$ is the lift size. (a) Tanner graph of a hypergraph product code, constructed from a product of two classical codes. Empty blue circles and purple squares represent the data and check bits of the classical codes, respectively. (b) Tanner graph of a quasi-cyclic lifted product code. Each edge is assigned a monomial $x^s$ ($s\in[l]$, $x^l=1$). (c) Example of unraveling the edge between two lifted nodes ($l=12$). (d)(e) Tanner graph of a balanced product cyclic code. Each edge is assigned a polynomial with terms $x^s$. In (d), vertical edges have a one-to-one mapping. In (e), the qubits are "shuffled" within each quadrant such that horizontal edges have a one-to-one mapping.
  • Figure 3: Syndrome extraction circuit.(a) A qubit 4-cycle, or a cycle of (data qubit)-(Z syndrome qubit)-(data qubit)-(X syndrome qubit), should consist of edges of all 4 directions. We use the convention in Ref. tremblay2022constant and set the ordering of the directions as E$\rightarrow$N$\rightarrow$S$\rightarrow$W. (b) Assignment of the signs of the classical Tanner graph's edges, which determines the directions of the quantum Tanner graph's edges. Note that the colors represent the directions as matched in (a) and are irrelevant to the edge coloration. (c)(d) Directions of the edges in a BPC code's Tanner graph. Horizontal edges are assigned directions E and W in (c), and vertical edges are assigned directions N and S in (d).
  • Figure 4: Space-time decoding graph. Tanner graph constructed from a detector error matrix. Each square represents a detector. Each circle represents a possible error mechanism. Filled circles are errors that occur. Filled squares are the detectors flipped by the errors. For simplicity, we show a phenomenological noise model where there are only data qubit errors (blue circles) and measurement errors (light blue circles on the vertical edges). Dashed gray lines mark the time-like boundary of the decoding graph, which connects error mechanisms to detectors of future time steps they support. (a)(b) Two possible combinations of errors that create the same detector flips. If single-shot error correction is performed and the error shown in (a) occurs, a minimum-weight decoder will apply the correction shown in (b) as it is the error combination with the lowest weight that produces the given flipped detector set. (c) A decoding window for a $(5,3)$ sliding-window decoding. For each decoding window, we pass the detector flips of $W$ consecutive time steps to an inner decoder. Based on the correction suggested by the inner decoder, we apply the correction that flips the detectors in the first $F$ time steps. By increasing the size of the decoding window, more detector information is included in the decoding window. Thus, the decoder can correct the error shown in (a) that occurs at the beginning of the decoding window.
  • Figure 5: LFR simulation. Logical memory simulations of various QLDPC codes under the standard circuit-level depolarizing noise model using a $(5,3)$ space-time sliding-window decoding with a BP-OSD inner decoder. The error bars represent the 95% confidence interval. Reference curves are drawn for the comparison of effective distances $d_{\rm eff}$. (a) HGP code simulation. A threshold is identified at approximately $0.23\%$ for circuits with syndrome extraction depth $d_c=12$. Note that the $[[225,9,6]]$ HGP code with $d_c = 8$ outperforms all HGP codes implemented with a $d_c = 12$ circuit in the high-error region and exhibits comparable performance to the $[[900,36,10]]$ code with a $d_c = 12$ circuit as $p$ decreases. (b) QLP code simulation. A threshold is identified at approximately $0.24\%$. Notably, an error floor behavior is observed for the QLP code. This is evident as the slopes of the curves reduce, showing no clear dependence on the code size. This error floor is likely caused by small cycles in the space-time detector error matrix, which hinder the convergence of BP. (c) BPC code simulation. A threshold is observed at approximately $0.47\%$. The slopes of the curves suggest that our circuits maintain $d_{\rm eff}$ comparable to $d$ for the simulated range of $p$.
  • ...and 1 more figures