Geometric Programming for 3D Circuits
Rongbiao Wang, Lek-Heng Lim
TL;DR
The paper tackles the challenge of designing high-performance full 3D integrated circuits by formulating floorplanning, transistor sizing, and interconnect sizing as generalized geometric programs (GGPs) that are solved via convex GP after a log-domain transformation, providing global-optimal solutions. It introduces a temperature-aware floorplanning framework, a GP-based transistor sizing model with ISCAS-85 benchmarks showing substantial delay reductions, and an RC-tree interconnect sizing approach that reveals a critical interconnect width threshold governing delay improvements. The work presents the first systematic GP-based treatment of full 3D integration, offering a unified, scalable optimization framework and accompanying code for practitioners. This approach enables rapid, data-driven design iterations as 3D architectures and device technologies evolve, with the potential to substantially reduce volume, delay, and thermal performance gaps in next-generation ICs.
Abstract
With the soaring demand for high-performing integrated circuits, 3D integrated circuits (ICs) have emerged as a promising alternative to traditional planar structures. Unlike existing 3D ICs that stack 2D layers, a full 3D IC features cubic circuit elements unrestricted by layers, offering greater design freedom. Design problems such as floorplanning, transistor sizing, and interconnect sizing are highly complex due to the 3D nature of the circuits and unavoidably require systematic approaches. We introduce geometric programming to solve these design optimization problems systematically and efficiently.