An improved update rule for probabilistic computers

TL;DR

The work addresses the challenge of efficiently simulating probabilistic Ising-type networks (P-Bits) on CMOS hardware, especially for reverse-mode tasks like semiprime factorization. It introduces a discretized update rule m_i = RNG(b) sgn(I_i) with $I_i = \sum_j J_{ij} m_j + h_i$ and $b = (1+|\tanh(\beta I_i)|)/2$, leveraging tanh saturation, LUT-based sign decisions, and sparsification ($M\le 5$) to enable resource-efficient FPGA implementations. An unbiased RNG ensemble is combined via an $R$-input AND to realize the biased randomness, with LFSRs providing the random bits; this suite yields dramatic reductions in on-chip LUTs/FFs and clock-rate constraints while sustaining correct Boltzmann-like behavior. The method is demonstrated on reverse-mode gates (AND, FA) and extended to sparsified binary multipliers for semiprime factorization, achieving up to $2.29\times 10^{11}$ FPS for 16×16 multipliers and factorization of a 32-bit semiprime in roughly $100$ seconds, with exponential scaling in problem size. The results indicate a practical path to new probabilistic hardware realizations and broaden the applicability of P-Bit networks to other combinatorial problems such as Max-Cut and 3-SAT.

Abstract

Many hard combinatorial problems can be mapped onto Ising models, which replicate the behavior of classical spins. Recent advances in probabilistic computers are characterized by parallelization and the introduction of novel hardware platforms. An interesting application of probabilistic computers is to operate them in `reverse' mode, where the network self-organizes its behavior to find the input bits that result in an output state. This can be used, for example, as a factorizer of semiprimes. One issue with simulating probabilistic computers on standard logic devices, such as field-programmable gate arrays, is that the update rules for each spin involve many multiplications, evaluation of a hyperbolic tangent, and a high-resolution numerical comparison. We simplify these rules, which improves the spatial and temporal circuit complexity when simulating a probabilistic computer on a field-programmable gate array. Applying our method to factorizing semiprimes, we achieve at least an order-of-magnitude reduction in the on-chip resources and the time-to-solution compared to recently reported methods. For a 32-bit semiprime, we achieve an average factorization in $\sim$100 s. Our approach will inspire new physical realizations of probabilistic computers because we relax some of their update-rule requirements.

Figures (11)

• Figure 1: P-Bit network finds an energy minima. a) A simplified illustration of the energy landscape, where the horizontal dimensions are a flattened N-dimensional $\bm{m}$. The red balls are the energies of given states, the solid line is an energetically unfavorable spin flip, and the dashed line is an energetically favorable flip. b) Typical update rules' continuous spin-flip probabilities. c) Our discretized and truncated spin-flip probabilities.
• Figure 2: Previous P-Bit simulation circuits. Typical circuitry required on an FPGA to update the $i$th P-Bit. The gray circles are multipliers, and the bit-widths of each value are given (adapted from Aadit2022).
• Figure 3: AND gate. a) Typical circuit depiction. b) Probabilistic formulation, with weight and bias terms in binary form. LUT for updating output P-Bit c) $C$, d) $A$, where the ambiguity (?) corresponds to equal probability of $A=0$ and $A=1$, and e) $B$, which is symmetric to d).
• Figure 4: AND gate experiments. Frequency diagram when running the AND gate in reverse mode, with P-Bit $C$ clamped to 0, sampled after each of the 131,072 full system updates. The orange dots show the Bolztmann probabilities given by Eq. (\ref{['Eq:probs']}).
• Figure 5: Full-adder. a) Typical circuit diagram. b) Probabilistic formulation, with weights and biases in binary form. c) Example input (A,B,C$_{\textrm{in}}$) state evolution in reverse mode, initial condition $= \{1,0,1\}$, outputs clamped to {S,C$_{\textrm{out}}$}={0,1}. Dotted lines are energetically unfavorable flips (with $I_i=\pm1$). Solid lines are energetically favorable flips.