Machine Learning-assisted High-speed Combinatorial Optimization with Ising Machines for Dynamically Changing Problems

TL;DR

The paper tackles dynamically changing combinatorial optimization problems that require rapid sequential solutions. It introduces a hardware-software stack built around simulated bifurcation (SB) based Ising machines, implemented on FPGA/CPU, with indexing fast-computation architecture and ML-driven parameter estimation to adapt to varying problem sizes. The MIS/TDMA demonstrations show substantial system-wide latency reductions and robustness, achieving orders-of-magnitude speedups over conventional solvers and underscoring practical applicability in real-time network scheduling. This work advances the deployment of Ising-machine–based optimization in time-sensitive domains by tightly integrating hardware acceleration, data compression, and learning-based control.

Abstract

Quantum or quantum-inspired Ising machines have recently shown promise in solving combinatorial optimization problems in a short time. Real-world applications, such as time division multiple access (TDMA) scheduling for wireless multi-hop networks and financial trading, require solving those problems sequentially where the size and characteristics change dynamically. However, using Ising machines involves challenges to shorten system-wide latency due to the transfer of large Ising model or the cloud access and to determine the parameters for each problem. Here we show a combinatorial optimization method using embedded Ising machines, which enables solving diverse problems at high speed without runtime parameter tuning. We customize the algorithm and circuit architecture of the simulated bifurcation-based Ising machine to compress the Ising model and accelerate computation and then built a machine learning model to estimate appropriate parameters using extensive training data. In TDMA scheduling for wireless multi-hop networks, our demonstration has shown that the sophisticated system can adapt to changes in the problem and showed that it has a speed advantage over conventional methods.

Figures (8)

• Figure 1: A dynamically changing problem that include sequential combinatorial optimization and a combinatorial optimization system using embeddable Ising machines. The system contains modules for low latency computation (blue-highlighted) and modules for scalability and diversification (green-highlighted) to handle the sequential problems having various sizes and characteristics.
• Figure 2: Indexing fast-computation architecture. (a) Distributions of $J$-matrix element values in Ising models, representing various combinatorial optimization problems. (b) The method of indexing. An indexed $J$-Table is generated by extracting distinct values from the distribution of the $J$-matrix and then assign an index for each value. By replacing the real values in the original $J$-matrix with the corresponding indices, a smaller-sized indexed $J$-matrix is produced. (c) A system utilizing the encoding method. The indexed $J$ accelerates data transfer speed between the CPU and the Ising machine, and also reduces the memory requirements for the Ising machine. (d) Indexed J-specialized MAC for simulated bifurcation (SB). By factorizing a MAC (multiply and accumulation) operation to isolate the additive part of the position variables x, most computations can be performed without decoding the indexed J from indices to real values, leading to faster computation.
• Figure 3: ML-assisted scalable and diversified architecture. The MIS (maximum independent set) problem is chosen as a motif. (a) Preparation of the training dataset. Generate 2840 random graphs based on three different basic structures. Using an Ising machine-based MIS solver, perform a grid search to find the Ising machine parameters that can produce the best independent set for each graph more quickly. Record the best parameters with graph features in the dataset. (b) ML-based parameter estimator trained based on a XGBoost regression model. The 3D graph visualizes the response of $steps$ to $N$ and $density$, with the values of $average\ degree$ and $Gini$ fixed. (c) System architecture, which comprises multiple Ising machines (FPGA/CPU-implmented), a machine selector, a parameter estimator, and a batch mapper. By using the machine selector and the parameter estimator, one of Ising machines and the control paramters for the Ising machine are selected for each graph (problem) depending on the graph features. A batch processing mechanism to efficiently solves small problems with the fixed-size FPGA-based Ising machine is also equipped. (d) Performance comparison of the three MIS solvers based on SB (heuristic, this work), NetworkX (heuristic), and OR-Tools (exact-solution), showing the number of independent sets (#IS) $\uparrow$ versus the computation time $\downarrow$ for various sizes and characteristics of graphs with edge densities $p$ (0.1, 0.4, 0.8) and node numbers $|V|$ (2000, 500, 100, 20). Each data point represents the mean value of #IS and computation time with error bars indicating the standard deviation for five instances. The legend in the bottom-right graph applies to all four graphs.
• Figure 4: Demonstration of TDMA scheduling in wireless multi-hop networks. (a) An example of transmission paths with a tree topology. Each sensor sends its data to its parent node, and eventually, the data from all sensors is collected at the base station (BS). (b) An example of interference as a constraint. Consider a situation where data is being transmitted from node 1 to node 2 and simultaneously from node 3 to another node. If node 2 in the receiving state is in the communication radius r centerded at node 1 and node 3, the interference of the multiple signals happens. (c) TDMA scheduling procedure. Nodes are iteratively assigned to time slots (the $k$-th TDMA slot) based on interference constraints. The tree graph shrinks as leaf nodes are removed at each iteration. The maximum independent set (MIS) of the subgraph $G$, formed by leaf nodes, is found for each time slot, and these nodes are scheduled and removed from the tree graph. This process repeats until all nodes are scheduled. (d) Experimental setup. $N_s$ sensor nodes placed randomly in a $1.0 \times 1.0$ field, with low interference fields (L.I.F) and high interference fields (H.I.F). The communication radius $r$ varies to create different interference levels. (e) The total number of TDMA slots (#slots$\downarrow$) versus the computation time$\downarrow$ for simulated bifurcation (SB)-based and NetworkX (NX)-based MIS solvers when changing the number of sensor nodes ($N_s$) and the communication radius ($r$). (f) Transition of graph features (edge density, average degree, Gini coefficient) and selected Ising machine parameters ($c$, $dt$, $step$), as well as the decision on which Ising machine to use, during iterations for $N_s = 2000$ in H.I.F. The light-colored area indicates the FPGA-based Ising machine is selected, while the dark-colored area indicates the CPU-based Ising machine is chosen.
• Figure 5: FPGA implementation of the Ising machine. (a) Circuit architecture of the bSB using indexing fast-computing ($N_v=2$, with TBL[1] reserved as 0). (b) Implementation details of the SB-based Ising machine. (c) Placement of the Ising machine in the FPGA.