Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

TL;DR

Problem: energy-constrained general-purpose accelerators struggle to sustain high IPC on lean in-order cores when workloads mix integer and floating-point operations. Approach: COPIFT introduces a six-step methodology to partition, schedule, tile, and pipeline computations, plus ISA extensions to support inter-thread dependencies, enabling sustained dual-issue execution on the Snitch core. Contributions: a complete COPIFT framework with ISA extensions, an open-source Snitch implementation, and empirical results showing average speedups of $1.47\times$ and energy reductions of $1.37\times$ (peak $1.93\times$) across mixed workloads. Significance: demonstrates practical dual-issue execution for mixed workloads on energy-efficient in-order cores, informing design tradeoffs for general-purpose accelerators.

Abstract

To meet the computational requirements of modern workloads under tight energy constraints, general-purpose accelerator architectures have to integrate an ever-increasing number of extremely area- and energy-efficient processing elements (PEs). In this context, single-issue in-order cores are commonplace, but lean dual-issue cores could boost PE IPC, especially for the common case of mixed integer and floating-point workloads. We develop the COPIFT methodology and RISC-V ISA extensions to enable low-cost and flexible dual-issue execution of mixed integer and floating-point instruction sequences. On such kernels, our methodology achieves speedups of 1.47x, reaching a peak 1.75 instructions per cycle, and 1.37x energy improvements on average, over optimized RV32G baselines.

Figures (4)

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• Figure 8: Comparison of various metrics between COPIFT and baseline codes. Dashed lines indicate expected values: (a) the derived from $I'$ and (c) the speedup $S'$.
• Figure 9: of the poly_lcg kernel for various problem and block sizes.