Simplifier: A New Tool for Boolean Circuit Simplification

TL;DR

This work tackles the Boolean circuit simplification problem by introducing Simplifier, a low-effort open-source tool that targets $3$-input, up to $3$-output subcircuits. It combines a precomputed database of optimized subcircuits with linear-time enumeration of 3-principal subcircuits to achieve fast, local transformations that reduce circuit size. Empirically, Simplifier yields an average size reduction of $4\%$ on AIG circuits after applying the ABC framework and $30\%$ on BENCH circuits, demonstrating practical gains and complementing existing tooling. The approach emphasizes efficiency and practicality, providing a scalable option for industrial and handcrafted circuits in both AIG and BENCH formats.

Abstract

The Boolean circuit simplification problem involves finding a smaller circuit that computes the same function as a given Boolean circuit. This problem is closely related to several key areas with both theoretical and practical applications, such as logic synthesis, satisfiability, and verification. In this paper, we present Simplifier, a new open source tool for simplifying Boolean circuits. The tool optimizes subcircuits with three inputs and at most three outputs, seeking to improve each one. It is designed as a low-effort method that runs in just a few seconds for circuits of reasonable size. This efficiency is achieved by combining two key strategies. First, the tool utilizes a precomputed database of optimized circuits, generated with SAT solvers after carefully clustering Boolean functions with three inputs and up to three outputs. Second, we demonstrate that it is sufficient to check a linear number of subcircuits, relative to the size of the original circuit. This allows a single iteration of the tool to be executed in linear time. We evaluated the tool on a wide range of Boolean circuits, including both industrial and hand-crafted examples, in two popular formats: AIG and BENCH. For AIG circuits, after applying the state-of-the-art ABC framework, our tool achieved an additional 4% average reduction in size. For BENCH circuits, the tool reduced their size by an average of 30%.

Figures (3)

• Figure 1: Four representations of the function $x_1 \oplus x_2 \oplus x_3 \oplus x_4 \oplus x_5$: a truth table, a CNF, a circuit over the full binary basis $B_2$ of size $4$, and a circuit over $\{\neg, \land\}$ of size $12$ (for the circuits, the dashed wires are negated, the output gate is shown in bold). Each of the shown representations is known to be optimal with respect to its size.
• Figure 2: Examples of circuit simplification: removing dangling gates (left) and merging duplicate gates (right).
• Figure 3: Two circuits, of size $7$ and $5$, computing the binary representation of the sum of three input bits.