Semicustom Frontend VLSI Design and Analysis of a 32-bit Brent-Kung Adder in Cadence Suite

TL;DR

The paper addresses the need for fast, scalable addition in digital VLSI by designing and simulating a 32‑bit Brent‑Kung parallel‑prefix adder. It implements a modular Verilog RTL with Preprocessing, Black/Gray prefix cells, and Postprocessing, and validates the design through functional testbenches and Cadence Genus synthesis. Key results include a critical path of $3.78$ ns, area $1223.91~\mu m^2$, and total power $43.32~\mu$W, with a comparative analysis showing clear speed advantages over RCA and CLA while balancing hardware complexity against KSA/SKSA. The work demonstrates a practically attractive semicustom frontend approach for high‑speed arithmetic and provides source access via GitHub, highlighting its relevance for modern digital systems requiring efficient carry propagation.

Abstract

Adders are fundamental components in digital circuits, playing a crucial role in arithmetic operations within computing systems and many other applications. This paper focuses on the design and simulation of a 32-bit Brent-Kung parallel prefix adder, which is recognized for its efficient carry propagation and logarithmic delay characteristics. The Brent-Kung architecture balances computational speed and hardware complexity, making it suitable for high-speed digital applications. The design is implemented using Verilog HDL and simulated using Cadence Design Suite tools, including NCLaunch and Genus, to evaluate its performance in terms of scalability, speed, and functional working. Comparative analysis with traditional adder architectures highlights the advantages of the Brent-Kung adder for modern digital systems.

Figures (18)

• Figure 1: Half-Adder Logic Gate Implementation
• Figure 2: Full-Adder Logic Gate Implementation
• Figure 3: Ripple Carry Adder
• Figure 4: Carry Look Ahead Adder
• Figure 5: Brent Kung Adder (16 bit)