P4sim: Programming Protocol-independent Packet Processors in ns-3

TL;DR

P4sim addresses the need for high-performance, protocol-independent P4 simulation within ns-3 by integrating bmv2 and NS4, extending support to V1model, PSA, and PNA. It introduces a time-aware switch model, advanced queueing, and a protocol-independent custom-header framework to enable realistic data-plane experimentation and seamless host-switch interaction. The paper details the design and implementation of P4SwitchNetDevice, P4SwitchCore, and CustomHeader/CustomP2PNetDevice, and validates the approach through throughput benchmarks and two use cases: Basic Tunneling and Load Balancing. The results demonstrate viable performance and flexibility for programmable-network research and education, while outlining future work on queue-state feedback and deeper hardware-timing integration.

Abstract

Programmable data planes enable users to design data plane algorithms for network devices, providing extensive flexibility for network customization. Programming Protocol-Independent Packet Processors (P4) has become the most widely adopted abstraction, programming language, and framework for data plane programming. However, existing simulation platforms lack high-performance support for P4-based networks. This paper introduces P4sim, a high-performance P4-driven simulation framework built on bmv2 and NS4, seamlessly integrated with ns-3. It improves queue modeling, time scheduling, and P4 architecture support, extending compatibility to V1model, PSA, and PNA. P4sim enables efficient packet processing, accurate time tracking, and seamless interaction between P4-enabled hosts and switches. We evaluate the P4sim in terms of performance and queue management and demonstrate its capabilities using two common use cases: Basic Tunneling and Load Balancing. The results highlight the P4sim as a powerful tool for advancing research and education in programmable networks.

Figures (8)

• Figure 1: Internal structure of the proposed P4 switch model implemented in ns-3, following the PSA architecture. The figure illustrates two key aspects: the packet processing pipeline configured via the P4 program, and the buffer management and scheduling mechanisms configured within ns-3.
• Figure 2: Example of the packet with tunnel custom header.
• Figure 3: UML diagram of the P4 switch implementation, showing only the important newly added classes, functions, and variables.
• Figure 4: Evaluation of network performance through packet forwarding.
• Figure 5: Evaluation of simulation efficiency based on wall-clock execution time.