CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems

TL;DR

This work describes an open-source tool, CATCH, that can be used to guide early design choices regarding the number of chiplets, the design partitions, the interconnect types, and other factors that must be made early in the development process.

Abstract

With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to a single die design, now there are options for 2.5D and 3D stacking along with a plethora of choices regarding configurations and processes. For chiplet-based designs, high-impact decisions such as those regarding the number of chiplets, the design partitions, the interconnect types, and other factors must be made early in the development process. In this work, we describe an open-source tool, CATCH, that can be used to guide these early design choices. We also present case studies showing some of the insights we can draw by using this tool. We look at case studies on optimal chip size, defect density, test cost, IO types, assembly processes, and substrates.

Figures (21)

• Figure 1: Supported Structures. The tool can model any arbitrary 2.5D or 3D stack of Chip objects provided that a larger die is not placed on top of multiple smaller dies.
• Figure 2: IO Pad Placement
• Figure 3: Multiple IO Type Pad Placement
• Figure 4: Stackup Options. It is possible to define the characteristics of a die either as a single Layer or as a stack of Layers.
• Figure 5: The die per wafer calculation will increase the number of dies in the first column iteratively and fit around that. The best of these will be selected as the solution. In this example, the best case was 4 dies in the first column with a total of 108 dies per wafer. This did not run past 6 dies in the first column as 7 would allow enough room for another column to the left and would look like one of the previous cases.