Kolmogorov-Arnold Network for Transistor Compact Modeling

TL;DR

The paper tackles the interpretability bottleneck in neural-network–based transistor compact modeling by introducing Kolmogorov-Arnold Network (KAN) and Fourier KAN (FKAN) to achieve both precision and symbolic interpretability. It benchmarks these architectures against the industry-standard BSIM-CMG and MLP on 7 nm FinFET data, examining ID, QD, and QS predictions and exploring symbolic regression capabilities. Key contributions include the design of edge-activated, spline- and Fourier-based KANs, a comprehensive experimental framework with multiple datasets, and an iterative symbolic-regression approach to extract interpretable formulas. While KANs can deliver high prediction accuracy, derivative behavior poses challenges for circuit-level simulations, highlighting a need for domain-knowledge-guided refinements to realize fully interpretable, scalable transistor models for advanced technology nodes.

Abstract

Neural network (NN)-based transistor compact modeling has recently emerged as a transformative solution for accelerating device modeling and SPICE circuit simulations. However, conventional NN architectures, despite their widespread adoption in state-of-the-art methods, primarily function as black-box problem solvers. This lack of interpretability significantly limits their capacity to extract and convey meaningful insights into learned data patterns, posing a major barrier to their broader adoption in critical modeling tasks. This work introduces, for the first time, Kolmogorov-Arnold network (KAN) for the transistor - a groundbreaking NN architecture that seamlessly integrates interpretability with high precision in physics-based function modeling. We systematically evaluate the performance of KAN and Fourier KAN for FinFET compact modeling, benchmarking them against the golden industry-standard compact model and the widely used MLP architecture. Our results reveal that KAN and FKAN consistently achieve superior prediction accuracy for critical figures of merit, including gate current, drain charge, and source charge. Furthermore, we demonstrate and improve the unique ability of KAN to derive symbolic formulas from learned data patterns - a capability that not only enhances interpretability but also facilitates in-depth transistor analysis and optimization. This work highlights the transformative potential of KAN in bridging the gap between interpretability and precision in NN-driven transistor compact modeling. By providing a robust and transparent approach to transistor modeling, KAN represents a pivotal advancement for the semiconductor industry as it navigates the challenges of advanced technology scaling.

Figures (8)

• Figure 1: architecture (a), compared to architecture (b), employs learnable activation functions on edges instead of weights.
• Figure 2: Activation functions in are parameterized $k$-order B-spline curves $\phi(x)$ with learnable coefficients $c_i$ of B-spline basis functions $B_i$. This implementation provides adaptive non-linearity and allows a better fit for complex physics-based functions.
• Figure 3: Mean absolute percentage train (red) and test (blue) error (MAPE), calculated against industry-standard compact model. The comparison on various datasets from Table \ref{['table:data_overview']} for smaller (top) and bigger (bottom) networks shows KANs' remarkable fitting accuracy over MLPs and FKANs, while highlighting poor $I_{\text{D}}$ generalization and lower consistency. Network names are architectures from Table \ref{['table:net_overview']}. Boxes correspond to 25,75 percentiles and represent consistency. The median value is illustrated with a middle line within each box. Whiskers show the minimum and the maximum error achieved by networks. Test MAPE for $I_{\text{D}}$ and $50mV$ step in KAN1 and KAN2 cases exceeds plot limits and is not shown for better general visibility.
• Figure 4: Transconductance (top) and its derivative (bottom) for networks MLP2, KAN2, and FKAN2 compared against the industry-standard compact model simulated in SPICE (dashed lines). Network names are architectures from Table \ref{['table:net_overview']}. Since transistors are usually biased around the peak $g_m$ region for higher gain, the slight deviation in the higher-voltage region for is less important. However, due to inherent properties, and demonstrate a faulty derivative behavior, which will affect circuit simulations.
• Figure 5: symbolic regression for $Q_{\text{S}}$ modeling. Plot intensity on the left figure represents the importance of nodes/edges for the output and shows the essential parts for $Q_{\text{S}}$ modeling, corresponding to $V_G$.