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Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging

Partho Bhoumik, Christopher Bailey, Krishnendu Chakrabarty

TL;DR

This work tackles defect analysis in Fan-out Wafer-Level Packaging (FOWLP) chiplet interconnects by mapping thermo-mechanical and manufacturing defects to equivalent RC circuits using Ansys Q3D, and by conducting fault simulations to identify when such defects cause functional failure. It introduces a BIST architecture that detects and diagnoses stuck-at and bridging faults with only three test patterns, achieving about 95–96% diagnosability, and couples defect simulations with test outcomes to estimate deformity ranges in Cu pillars and RDLs. A control framework with block-level testing and PPA assessment demonstrates trade-offs between area, power, and test time for AES/DES benchmarks, guiding design-for-test decisions in multi-chiplet packages. Overall, the approach enables lifecycle monitoring and robust design decisions for FOWLP interconnects by linking physical defect characteristics to circuit-level behavior and testability metrics.

Abstract

Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP faces manufacturing challenges such as coefficient of thermal expansion (CTE) mismatch, warpage, die shift, and post-molding protrusion, causing misalignment and bonding issues during redistribution layer (RDL) buildup. Moreover, the organic nature of the package exposes it to severe thermo-mechanical stresses during fabrication and operation. In order to address these challenges, we propose a comprehensive defect analysis and testing framework for FOWLP interconnects. We use Ansys Q3D to map defects to equivalent electrical circuit models and perform fault simulations to investigate the impacts of these defects on chiplet functionality. Additionally, we present a built-in self-test (BIST) architecture to detect stuck-at and bridging faults while accurately diagnosing the fault type and location. Our simulation results demonstrate the efficacy of the proposed BIST solution and provide critical insights for optimizing design decisions in packages, balancing fault detection and diagnosis with the cost of testability insertion.

Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging

TL;DR

This work tackles defect analysis in Fan-out Wafer-Level Packaging (FOWLP) chiplet interconnects by mapping thermo-mechanical and manufacturing defects to equivalent RC circuits using Ansys Q3D, and by conducting fault simulations to identify when such defects cause functional failure. It introduces a BIST architecture that detects and diagnoses stuck-at and bridging faults with only three test patterns, achieving about 95–96% diagnosability, and couples defect simulations with test outcomes to estimate deformity ranges in Cu pillars and RDLs. A control framework with block-level testing and PPA assessment demonstrates trade-offs between area, power, and test time for AES/DES benchmarks, guiding design-for-test decisions in multi-chiplet packages. Overall, the approach enables lifecycle monitoring and robust design decisions for FOWLP interconnects by linking physical defect characteristics to circuit-level behavior and testability metrics.

Abstract

Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP faces manufacturing challenges such as coefficient of thermal expansion (CTE) mismatch, warpage, die shift, and post-molding protrusion, causing misalignment and bonding issues during redistribution layer (RDL) buildup. Moreover, the organic nature of the package exposes it to severe thermo-mechanical stresses during fabrication and operation. In order to address these challenges, we propose a comprehensive defect analysis and testing framework for FOWLP interconnects. We use Ansys Q3D to map defects to equivalent electrical circuit models and perform fault simulations to investigate the impacts of these defects on chiplet functionality. Additionally, we present a built-in self-test (BIST) architecture to detect stuck-at and bridging faults while accurately diagnosing the fault type and location. Our simulation results demonstrate the efficacy of the proposed BIST solution and provide critical insights for optimizing design decisions in packages, balancing fault detection and diagnosis with the cost of testability insertion.

Paper Structure

This paper contains 14 sections, 1 theorem, 9 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Fan-out Wafer Level Packaging
  4. Finite Element Analysis
  5. Defect Analysis
  6. Defects and Equivalent Circuits
  7. Fault-free RLC Extraction and Equivalent Circuit
  8. Ansys Modeling and Equivalent Faulty Circuits
  9. Simulation Results
  10. Fault Analysis
  11. BIST Solution
  12. Detection and Diagnosis
  13. Control Architecture and PPA Assessment
  14. Conclusion

Key Result

Theorem 1

The three test patterns shown in Fig. fig:detection(a) can detect all SAFs and bridging faults associated with interconnects between chiplets. In addition, these patterns can distinguish between any pair of faults with an accuracy of 95.61%.

Figures (9)

  • Figure 1: Illustration of a fully molded FOWLP structure rogers2013implementation.
  • Figure 2: Equivalent nominal and faulty circuits for Cu pillars and RDL.
  • Figure 3: Ansys modeling of Cu pillars and RDL.
  • Figure 4: Extracted parasitics for defects in: (a) cracked pillars; (b) shorted pillars; (c) capacitive misalignment; (d) resistive misalignment; (e) damaged RDL; (f) shorted RDL.
  • Figure 5: HSPICE setup for package-level fault simulation.
  • ...and 4 more figures

Theorems & Definitions (2)

  • Theorem 1
  • proof