Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation

TL;DR

Open3DBench addresses the need for an open, reproducible benchmark to evaluate 3D-IC backend implementations and PPA metrics. It delivers an end-to-end 3D flow built on OpenROAD-flow-scripts, including 3D partitioning, placement, routing, RC extraction, and thermal analysis, and introduces two 3D placement strategies (Open3D-Tiling and Open3D-DMP) that show substantial gains in area, wirelength, timing, and power relative to 2D baselines. However, the work also reveals that wirelength optimization alone does not guarantee final PPA improvements in 3D contexts, highlighting the need for PPA-driven 3D methods. By providing an openly accessible, modular framework with PDK compatibility, Open3DBench helps bridge the gap between open-source tools and commercial flows for fair comparisons and broader community adoption.

Abstract

This work introduces Open3DBench, an open-source 3D-IC backend implementation benchmark built upon the OpenROAD-flow-scripts framework, enabling comprehensive evaluation of power, performance, area, and thermal metrics. Our proposed flow supports modular integration of 3D partitioning, placement, 3D routing, RC extraction, and thermal simulation, aligning with advanced 3D flows that rely on commercial tools and in-house scripts. We present two foundational 3D placement algorithms: Open3D-Tiling, which emphasizes regular macro placement, and Open3D-DMP, which enhances wirelength optimization through cross-die co-placement with analytical placer DREAMPlace. Experimental results show significant improvements in area (51.19%), wirelength (24.06%), timing (30.84%), and power (5.72%) compared to 2D flows. The results also highlight that better wirelength does not necessarily lead to PPA gain, emphasizing the need of developing PPA-driven methods. Open3DBench offers a standardized, reproducible platform for evaluating 3D EDA methods, effectively bridging the gap between open-source tools and commercial solutions in 3D-IC design.

Figures (8)

• Figure 1: The illustrations of micro-bumping, hybrid bonding, and monolithic 3D integration technologies are presented in subfigures (a), (b), and (c), respectively. The comparison of the dimensions of the three bonding vias is shown in subfigure (d).
• Figure 2: Comparison of routing wirelength (rWL), WNS, and TNS on design bp_be. Results generated by 2D and 3D flows using Hier-RTLMP-2D, Open3D-Tiling and Open3D-DMP methods for macro placement are presented in subfigures (a), (b), and (c), respectively. The red path highlights the most critical datapath, where the corresponding slack equals the WNS. All three paths originate from the same flip-flop and terminate at the same output port, indicated by a yellow circle.
• Figure 3: Overview of the proposed 3D backend implementation flow. The specific open-source tool adopted for each stage is marked in red.
• Figure 4: Illustration of our analytical pseudo-3D placement process. In each stage, the 2D placement is performed on the 2D plane framed by the solid line, where the components of the other die are integrated or projected onto the target die.
• Figure 5: Correlation analysis between rWL and key performance metrics comparing 2D and 3D methods. We plot the improvement ratio of the 3D method with the best rWL compared to the 2D method with the best rWL.