A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis

TL;DR

This paper tackles the challenge of systematic double-side clock tree synthesis (CTS) by leveraging back-side metal layers and nTSVs. It introduces a unified framework that combines hierarchical clock routing, concurrent insertion of buffers and nTSVs, skew refinement, and a design-space exploration flow based on multi-objective optimization. The approach yields substantial performance gains over state-of-the-art baselines in latency, skew, wirelength, and resource usage, while also offering significant runtime speed-ups. The work lays the groundwork for broader adoption of back-side CTS and points to future integration with placement and routing for a full-flow optimization.

Abstract

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest, several works have hacked existing backend tools to explore the potential of synthesizing double-side clock trees via nano Through-Silicon-Vias (nTSVs). However, these works lack a systematic perspective on design resource allocation and multi-objective optimization. We propose a systematic approach to design clock trees with double-side metal layers, including hierarchical clock routing, concurrent buffers and nTSVs insertion, and skew refinement. Compared with the state-of-the-art (SOTA) methods, the widely-used open-source tool, our algorithm outperforms them in latency, skew, wirelength, and the number of buffers and nTSVs.

Figures (12)

• Figure 1: Clock tree synthesis with double-side metal layers.
• Figure 2: Comparison between the buffered clock tree and the double-side clock trees by different methods to assign top and trunk nets to the back side.
• Figure 3: Delay modeling for buffer and nTSV insertion.
• Figure 4: Overview of our algorithm framework.
• Figure 5: Dual-level clustering and DME-based clock routing. Symbol "$\boldsymbol{+}$" refers to sink.