Table of Contents
Fetching ...

PLM: Efficient Peripheral Language Models Hardware-Co-Designed for Ubiquitous Computing

Cheng Deng, Luoyang Sun, Jiwen Jiang, Yongcheng Zeng, Xinjian Wu, Wenxin Zhao, Qingfa Xiao, Jiachuan Wang, Haoyang Li, Lei Chen, Lionel M. Ni, Haifeng Zhang, Jun Wang

TL;DR

PLM tackles the challenge of deploying language models on edge devices by co-designing architecture with hardware constraints. It introduces Multi-head Latent Attention to reduce KV-cache memory and a squared ReLU activation to promote sparsity, coupled with a WSDC-based training regimen and ARIES-style RLHF for alignment. With a total pre-training corpus of approximately 2.48 trillion tokens and additional instruction-focused post-training data, PLM-1.8B demonstrates competitive performance on a broad suite of benchmarks while maintaining low activated-parameter counts and strong edge-deployment viability. The work also provides extensive analysis of attention mechanisms and sparsity, and outlines concrete future directions for peripheral LLMs, including on-device adaptation, privacy-preserving learning, and edge-cloud collaboration.

Abstract

While scaling laws have been continuously validated in large language models (LLMs) with increasing model parameters, the inherent tension between the inference demands of LLMs and the limited resources of edge devices poses a critical challenge to the development of edge intelligence. Recently, numerous small language models have emerged, aiming to distill the capabilities of LLMs into smaller footprints. However, these models often retain the fundamental architectural principles of their larger counterparts, still imposing considerable strain on the storage and bandwidth capacities of edge devices. In this paper, we introduce the PLM, a Peripheral Language Model, developed through a co-design process that jointly optimizes model architecture and edge system constraints. The PLM utilizes a Multi-head Latent Attention mechanism and employs the squared ReLU activation function to encourage sparsity, thereby reducing peak memory footprint during inference. During training, we collect and reorganize open-source datasets, implement a multi-phase training strategy, and empirically investigate the Warmup-Stable-Decay-Constant (WSDC) learning rate scheduler. Additionally, we incorporate Reinforcement Learning from Human Feedback (RLHF) by adopting the ARIES preference learning approach. Following a two-phase SFT process, this method yields performance gains of 2% in general tasks, 9% in the GSM8K task, and 11% in coding tasks. In addition to its novel architecture, evaluation results demonstrate that PLM outperforms existing small language models trained on publicly available data while maintaining the lowest number of activated parameters. Furthermore, deployment across various edge devices, including consumer-grade GPUs, mobile phones, and Raspberry Pis, validates PLM's suitability for peripheral applications. The PLM series models are publicly available at https://github.com/plm-team/PLM.

PLM: Efficient Peripheral Language Models Hardware-Co-Designed for Ubiquitous Computing

TL;DR

PLM tackles the challenge of deploying language models on edge devices by co-designing architecture with hardware constraints. It introduces Multi-head Latent Attention to reduce KV-cache memory and a squared ReLU activation to promote sparsity, coupled with a WSDC-based training regimen and ARIES-style RLHF for alignment. With a total pre-training corpus of approximately 2.48 trillion tokens and additional instruction-focused post-training data, PLM-1.8B demonstrates competitive performance on a broad suite of benchmarks while maintaining low activated-parameter counts and strong edge-deployment viability. The work also provides extensive analysis of attention mechanisms and sparsity, and outlines concrete future directions for peripheral LLMs, including on-device adaptation, privacy-preserving learning, and edge-cloud collaboration.

Abstract

While scaling laws have been continuously validated in large language models (LLMs) with increasing model parameters, the inherent tension between the inference demands of LLMs and the limited resources of edge devices poses a critical challenge to the development of edge intelligence. Recently, numerous small language models have emerged, aiming to distill the capabilities of LLMs into smaller footprints. However, these models often retain the fundamental architectural principles of their larger counterparts, still imposing considerable strain on the storage and bandwidth capacities of edge devices. In this paper, we introduce the PLM, a Peripheral Language Model, developed through a co-design process that jointly optimizes model architecture and edge system constraints. The PLM utilizes a Multi-head Latent Attention mechanism and employs the squared ReLU activation function to encourage sparsity, thereby reducing peak memory footprint during inference. During training, we collect and reorganize open-source datasets, implement a multi-phase training strategy, and empirically investigate the Warmup-Stable-Decay-Constant (WSDC) learning rate scheduler. Additionally, we incorporate Reinforcement Learning from Human Feedback (RLHF) by adopting the ARIES preference learning approach. Following a two-phase SFT process, this method yields performance gains of 2% in general tasks, 9% in the GSM8K task, and 11% in coding tasks. In addition to its novel architecture, evaluation results demonstrate that PLM outperforms existing small language models trained on publicly available data while maintaining the lowest number of activated parameters. Furthermore, deployment across various edge devices, including consumer-grade GPUs, mobile phones, and Raspberry Pis, validates PLM's suitability for peripheral applications. The PLM series models are publicly available at https://github.com/plm-team/PLM.

Paper Structure

This paper contains 57 sections, 23 equations, 19 figures, 25 tables, 1 algorithm.

Figures (19)

  • Figure 1: System hardwares used in our experiments: (L-R) Broadcom (Raspberry Pi), NVIDIA Jetson Orin NX, Apple M3 (MacBook Air 2024), Qualcomm Snapdragon 8 Gen 3 (OnePlus 12 Pro), and the NVIDIA A10 experimental device is installed in the server.
  • Figure 2: Evaluations on LLM benchmarks demonstrate that our sparsified MLA models, PLM, maintain competitive performance. The performance is evidenced by the averaged benchmark scores in \ref{['expall']}, in terms of general knowledge comprehension (MMLU, CMMLU, C-Eval, ARC), Math problem solving (GSM8K and MathQA), coding proficiency (HumanEval and MBPP), and commonsense and logical reasoning (HellaSwag, BooQ, LogiQA, and PIQA). Meanwhile, the activated parameters are determined by the minimal computation required to preserve modeling performance. Detailed results are presented in \ref{['obsall']}.
  • Figure 3: PLM architecture.
  • Figure 4: Training pipeline adapted for PLM.
  • Figure 5: Pre-training loss curve for PLM.
  • ...and 14 more figures