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EDEA: Efficient Dual-Engine Accelerator for Depthwise Separable Convolution with Direct Data Transfer

Yi Chen, Jie Lou, Malte Wabnitz, Johnson Loh, Tobias Gemmeke

TL;DR

Depthwise separable convolution (DSC) enables efficient CNNs for edge devices, but balancing the workloads of depthwise (DWC) and pointwise (PWC) engines is challenging. The authors design a dual-engine ASIC with a Non-Convolutional Unit that fuses BN, ReLU, and quantization to minimize data movement and enable streaming operation, guided by a design-space exploration on MobileNetV1/CIFAR10. Post-layout results in 22 nm FDSOI show peak energy efficiency of $13.43$ TOPS/W and throughput of $973.55$ GOPS, with average efficiency and throughput of $11.13$ TOPS/W and $981.42$ GOPS across all layers, indicating substantial hardware efficiency gains for DSC-based networks. The approach is scalable to other DSC-based models and datasets, offering a practical path toward high-performance, energy-efficient edge AI accelerators.

Abstract

Depthwise separable convolution (DSC) has emerged as a crucial technique, especially for resource-constrained devices. In this paper, we propose a dual-engine for the DSC hardware accelerator, which enables the full utilization of depthwise convolution (DWC) and pointwise convolution (PWC) processing elements (PEs) in all DSC layers. To determine the optimal dataflow, data reuse, and configuration of the target architecture, we conduct a design space exploration using MobileNetV1 with the CIFAR10 dataset. In the architecture, we introduce an additional non-convolutional unit, which merges the dequantization, batch normalization (BN), ReLU, and quantization between DWC and PWC into a simple fixed-point multiplication and addition operation. This also reduces the intermediate data access between the DWC and PWC, enabling streaming operation and reducing latency. The proposed DSC dual-engine accelerator is implemented using the 22nm FDSOI technology from GlobalFoundries, occupying an area of 0.58 $mm^2$. After signoff, it can operate at 1 GHz at TT corner, achieving a peak energy efficiency of 13.43 TOPS/W with a throughput of 973.55 GOPS with 8-bit precision. The average energy efficiency of all DSC layers on MobileNetV1 is 11.13 TOPS/W, demonstrating substantial hardware efficiency improvements for DSC-based applications.

EDEA: Efficient Dual-Engine Accelerator for Depthwise Separable Convolution with Direct Data Transfer

TL;DR

Depthwise separable convolution (DSC) enables efficient CNNs for edge devices, but balancing the workloads of depthwise (DWC) and pointwise (PWC) engines is challenging. The authors design a dual-engine ASIC with a Non-Convolutional Unit that fuses BN, ReLU, and quantization to minimize data movement and enable streaming operation, guided by a design-space exploration on MobileNetV1/CIFAR10. Post-layout results in 22 nm FDSOI show peak energy efficiency of TOPS/W and throughput of GOPS, with average efficiency and throughput of TOPS/W and GOPS across all layers, indicating substantial hardware efficiency gains for DSC-based networks. The approach is scalable to other DSC-based models and datasets, offering a practical path toward high-performance, energy-efficient edge AI accelerators.

Abstract

Depthwise separable convolution (DSC) has emerged as a crucial technique, especially for resource-constrained devices. In this paper, we propose a dual-engine for the DSC hardware accelerator, which enables the full utilization of depthwise convolution (DWC) and pointwise convolution (PWC) processing elements (PEs) in all DSC layers. To determine the optimal dataflow, data reuse, and configuration of the target architecture, we conduct a design space exploration using MobileNetV1 with the CIFAR10 dataset. In the architecture, we introduce an additional non-convolutional unit, which merges the dequantization, batch normalization (BN), ReLU, and quantization between DWC and PWC into a simple fixed-point multiplication and addition operation. This also reduces the intermediate data access between the DWC and PWC, enabling streaming operation and reducing latency. The proposed DSC dual-engine accelerator is implemented using the 22nm FDSOI technology from GlobalFoundries, occupying an area of 0.58 . After signoff, it can operate at 1 GHz at TT corner, achieving a peak energy efficiency of 13.43 TOPS/W with a throughput of 973.55 GOPS with 8-bit precision. The average energy efficiency of all DSC layers on MobileNetV1 is 11.13 TOPS/W, demonstrating substantial hardware efficiency improvements for DSC-based applications.

Paper Structure

This paper contains 12 sections, 2 equations, 13 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Design Space Exploration
  3. Proposed Hardware Architecture
  4. Overall Architecture
  5. Dual Engines
  6. Non-Convolutional Unit
  7. Timing
  8. Experimental Results
  9. Latency and Power
  10. Energy Efficiency and Throughput
  11. Comparison with previous works
  12. Conclusion

Figures (13)

  • Figure 1: Data flow and tile mapping in DWC and PWC.
  • Figure 2: Design space exploration (a) PE array size (b) Activation and weight access count (upper bar: activation, lower bar: weight).
  • Figure 3: Activation access count and reduction percentage
  • Figure 4: Proposed system architecture.
  • Figure 5: DSC dual engines (a) DWC engine (b) PWC engine.
  • ...and 8 more figures