Review of Machine Learning for Micro-Electronic Design Verification

TL;DR

This survey analyzes how machine learning has been applied to dynamic, simulation-based verification of microelectronic designs, with emphasis on coverage closure, test generation/direction, and resource-efficient validation. It uncovers a historical shift from evolutionary algorithms toward supervised methods and notes a sustained but uneven industry adoption due to gaps in standard benchmarks, open datasets, and integration with existing verification environments. The review catalogs use cases, learning methodologies, and evaluation metrics, highlighting key benefits and pervasive challenges such as data quality, generalization, and the need for open benchmarks. It argues that progress will hinge on open datasets, common benchmarks, interoperability with verification tools, and cross-pollination with software verification insights to accelerate real-world deployment.

Abstract

Microelectronic design verification remains a critical bottleneck in device development, traditionally mitigated by expanding verification teams and computational resources. Since the late 1990s, machine learning (ML) has been proposed to enhance verification efficiency, yet many techniques have not achieved mainstream adoption. This review, from the perspective of verification and ML practitioners, examines the application of ML in dynamic-based techniques for functional verification of microelectronic designs, and provides a starting point for those new to this interdisciplinary field. Historical trends, techniques, ML types, and evaluation baselines are analysed to understand why previous research has not been widely adopted in industry. The review highlights the application of ML, the techniques used and critically discusses their limitations and successes. Although there is a wealth of promising research, real-world adoption is hindered by challenges in comparing techniques, identifying suitable applications, and the expertise required for implementation. This review proposes that the field can progress through the creation and use of open datasets, common benchmarks, and verification targets. By establishing open evaluation criteria, industry can guide future research. Parallels with ML in software verification suggest potential for collaboration. Additionally, greater use of open-source designs and verification environments can allow more researchers from outside the hardware verification discipline to contribute to the challenge of verifying microelectronic designs.

Figures (12)

• Figure 1: The role of dynamic based test methods within verification and validation. Adapted from ISO/IEC/IEEE 29119-2:2013, "Software and systems engineering — Software testing — Part 1: Concepts and definitions". The scope of the review is enclosed in the purple rectangle.
• Figure 2: Methodology used to filter search results.
• Figure 3: A conventional test bench used in the test-based verification of microelectronic designs. The test bench is configured for Coverage-Directed Generation using a parameterised stimuli generator and where human expertise (not machine learning) is used to control the generation of stimuli to the Design Under Verification (DUV).
• Figure 4: Number of papers by year and machine learning type.
• Figure 5: Verification activities using machine learning within the sampled research material for the functional verification of digital designs using dynamic-based methods.