Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach

TL;DR

This paper tackles the verification bottleneck in SoC designs by introducing a design-agnostic, ML-assisted workflow that optimizes coverage-driven simulation regressions. It integrates Python-based PyUVM testbenches with PyVSC coverage models and uses scikit-learn regression algorithms to predict constraint/sequence updates for hitting coverage bins, reducing test count and runtime. The authors demonstrate that several supervised models can attain about 99% coverage regain across three DUVs, with linear regression often providing the best performance, including a 99.5% regain on ADC. Automatic testbench updates translate ML outputs into actionable constraints and tests, enabling seamless integration and automation. Overall, the approach promises lower verification costs, less manual effort, and faster time-to-market.

Abstract

The escalating complexity of System-on-Chip (SoC) designs has created a bottleneck in verification, with traditional techniques struggling to achieve complete coverage. Existing techniques, such as Constrained Random Verification (CRV) and coverage-driven methodologies, rely on time-consuming and redundant simulation regression, leading to higher verification costs and longer time-to-market due to the manual effort required to adjust constraints and drive the stimuli to achieve coverage objectives. To address this challenge, we propose a novel methodology that leverages supervised Machine Learning (ML) to optimize simulation regressions, resulting in reduced simulation run-time and the number of test simulations required to achieve target coverage goals. We also investigate and compare the effectiveness of various supervised learning algorithms from scikit-learn. Our results demonstrate that these algorithms can achieve at least 99% coverage regain with significantly reduced simulation cycles. We utilize Python Universal Verification Methodology (PyUVM) over SystemVerilog-Universal Verification Methodology (SV-UVM) for testbench creation, enabling simpler constructs using Python and facilitating the reuse of existing ML libraries. Our methodology is applied to three diverse designs, and our results show that it can significantly reduce verification costs, manual efforts, and time-to-market, while enhancing verification productivity and completeness, by automating the testbench update process and achieving target coverage goals.

Figures (5)

• Figure 1: Proxy-driven PyUVM testbench
• Figure 2: Proposed methodology
• Figure 3: Data collection
• Figure 4: Data preparation
• Figure 5: Functional coverage with respect to test simulations generated by optimized regression