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Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language

Runzhi Wang, Prianka Sengupta, Cristhian Roman-Vicharra, Yiran Chen, Jiang Hu

TL;DR

Lorecast addresses the need for fast, layout-aware performance and power forecasts in early chip design stages by translating natural language prompts into Verilog code via LLMs and then forecasting post-routing power and timing (TNS) using an AST-based ML predictor. The method leverages Regulated Prompting with Implicit CoT (RePIC) and Iterative Prompting with Regulated Error Feedback (I-PREF) to ensure syntax correctness and stable code generation, while tolerating functional inaccuracies. Forecasts are produced with an XGBoost model trained on post-routing layout features, yielding near-ground-truth accuracy (≈$R^2=0.99$) and average errors around $2\%$, alongside substantial speedups (~$4.6\times$) compared with conventional HDL-based flows. This approach expands the practical use of LLM-generated HDL code in design space exploration, enabling rapid iteration and reduced reliance on expensive synthesis, even for large circuits.

Abstract

In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level models, which often lack accuracy, or trial synthesis, which is both labor-intensive and time-consuming. We introduce a new methodology, called Lorecast, which accepts English prompts as input to rapidly generate layout-aware performance and power estimates. This approach bypasses the need for HDL code development and synthesis, making it both fast and user-friendly. Experimental results demonstrate that Lorecast achieves accuracy within a few percent of error compared to post-layout analysis, while significantly reducing turnaround time.

Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language

TL;DR

Lorecast addresses the need for fast, layout-aware performance and power forecasts in early chip design stages by translating natural language prompts into Verilog code via LLMs and then forecasting post-routing power and timing (TNS) using an AST-based ML predictor. The method leverages Regulated Prompting with Implicit CoT (RePIC) and Iterative Prompting with Regulated Error Feedback (I-PREF) to ensure syntax correctness and stable code generation, while tolerating functional inaccuracies. Forecasts are produced with an XGBoost model trained on post-routing layout features, yielding near-ground-truth accuracy (≈) and average errors around , alongside substantial speedups (~) compared with conventional HDL-based flows. This approach expands the practical use of LLM-generated HDL code in design space exploration, enabling rapid iteration and reduced reliance on expensive synthesis, even for large circuits.

Abstract

In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level models, which often lack accuracy, or trial synthesis, which is both labor-intensive and time-consuming. We introduce a new methodology, called Lorecast, which accepts English prompts as input to rapidly generate layout-aware performance and power estimates. This approach bypasses the need for HDL code development and synthesis, making it both fast and user-friendly. Experimental results demonstrate that Lorecast achieves accuracy within a few percent of error compared to post-layout analysis, while significantly reducing turnaround time.

Paper Structure

This paper contains 17 sections, 4 equations, 14 figures, 8 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Background
  4. Large Language Models
  5. Verilog and Code Correctness
  6. The Proposed Lorecast Methodology
  7. Overview
  8. Phase I: LLM-Based Verilog Code Generation
  9. Phase II: Performance and Power Forecasting from Verilog Code
  10. Functional Correctness versus Structural Similarity
  11. Experimental Results
  12. Experiment Setup
  13. Main Results
  14. Importance of Syntax Correctness and Structural Similarity
  15. Impact of Functional Incorrectness
  16. ...and 2 more sections

Figures (14)

  • Figure 1: Traditional flow vs. proposed flow with Lorecast approach: from natural language to performance and power.
  • Figure 2: Overview of the Lorecast methodology.
  • Figure 3: The original description (left) and the template of RePIC (right).
  • Figure 4: RePIC pipeline: from RePIC prompt to Implicit CoT-guided Verilog code generation.
  • Figure 5: An example of a template for regulated feedback prompting.
  • ...and 9 more figures