Enhanced LPDDR4X PHY in 12 nm FinFET

TL;DR

This work presents a 12 nm FinFET LPDDR4X PHY that integrates a RISC-V subsystem to provide software-controlled DRAM access via a DFI Bridge and support for off-chip sensor interfaces. By moving beyond traditional read/write leveling, the design enables advanced monitoring and tuning of memory interfaces. The implemented architecture reaches up to 2133 MHz and includes a 1066 MHz RV32IMC processor connected through AXI4-Lite to SRAM, with detailed area and power metrics from a 12LPPlus process and a Nov 2023 tapeout. The results demonstrate feasibility and quantify power and area implications, highlighting potential improvements in memory reliability and system power through software-controlled interfacing. This work aids hardware designers and system integrators seeking deeper DRAM interfacing capabilities and sensor-based monitoring for LPDDR4X systems.

Abstract

The demand for memory technologies with high bandwidth, low power consumption, and enhanced reliability has led to the emergence of LPDDR4X DRAM memory. However, power efficiency and reliability depend not only on the memory device but also on its interfacing. To enable advanced monitoring of LPDDR4X DRAM devices and interface tuning, we propose a LPDDR4X PHY implemented in 12 nm FinFET technology. A RISC-V subsystem offers software-controlled DRAM interface access as well as external interfaces to connect additional sensors for monitoring temperature and current consumption of LPDDR4X DRAM devices.

Figures (4)

• Figure 1: LPDDR4X PHY Architecture
• Figure 2: RISC-V Subsystem Architecture
• Figure 3: lpddr phy Layout. Yellow outline marks the RISC-V Subsystem including the DFI Bridge.
• Figure 4: dfi Bridge Architecture