ARCAS: Adaptive Runtime System for Chiplet-Aware Scheduling

TL;DR

ARCAS tackles memory bandwidth saturation in chiplet-based CPUs by integrating chiplet-aware task scheduling, adaptive cache partitioning, and fine-grained coroutines with a lightweight performance profiler. The system dynamically migrates tasks to minimize inter-chiplet traffic while preserving data locality within chiplets, guided by runtime measurements. Empirical evaluation on a dual-socket AMD EPYC Milan platform shows ARCAS outperforms NUMA-aware baselines such as RING and SHOAL, with substantial speedups on graph processing and data-intensive workloads and strong scalability across core counts. This work demonstrates the practicality and impact of chiplet-aware runtime design for memory-bound parallel applications.

Abstract

The growing disparity between CPU core counts and available memory bandwidth has intensified memory contention in servers. This particularly affects highly parallelizable applications, which must achieve efficient cache utilization to maintain performance as CPU core counts grow. Optimizing cache utilization, however, is complex for recent chiplet-based CPUs, whose partitioned L3 caches lead to varying latencies and bandwidths, even within a single NUMA domain. Classical NUMA optimizations and task scheduling approaches unfortunately fail to address the performance issues of chiplet-based CPUs. We describe Adaptive Runtime system for Chiplet-Aware Scheduling (ARCAS), a new runtime system designed for chiplet-based CPUs. ARCAS combines chiplet-aware task scheduling heuristics, hardware-aware memory allocation, and fine-grained performance monitoring to optimize workload execution. It implements a lightweight concurrency model that combines user-level thread features-such as individual stacks, per-task scheduling, and state management-with coroutine-like behavior, allowing tasks to suspend and resume execution at defined points while efficiently managing task migration across chiplets. Our evaluation across diverse scenarios shows ARCAS's effectiveness for optimizing the performance of memory-intensive parallel applications.

Figures (13)

• Figure 1: ARCAS speedups compared to NUMA-aware systems across various benchmarks and workloads.
• Figure 2: AMD EPYC Milan.
• Figure 3: Cumulative Distribution Function (CDF) of core-to-core latency in an AMD EPYC Milan CPU.
• Figure 4: Number of memory channels vs. cores over the years.
• Figure 5: LocalCache vs. DistributedCache: write operation speedup when varying the data array size.