Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)

TL;DR

This work presents an MLIR-based, Julia-centric high-level synthesis flow that unifies algorithm and hardware development by automatically translating Julia code into Verilog. By extracting MLIR from Julia's rich type system and leveraging CIRCT for hardware generation, the approach supports both static and dynamic scheduling and aims to be open-source and easily extensible. The architecture separates front-end language mapping from back-end hardware lowering, enabling modular development and potential integration with existing HLS tooling. The authors outline a concrete roadmap toward broader language coverage, a Julia-wrapped CIRCT backend, rigorous evaluation, and formal verification to enhance reliability and adoption in scientific computing and accelerator design drivers.

Abstract

Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is too high for the majority of developers to overcome. We are developing a reusable end-to-end compiler toolchain for the Julia language entirely built on permissively-licensed open-source projects. This unifies accelerator and algorithm development by automatically synthesising Julia source code into high-performance Verilog.

Figures (1)

• Figure 1: Tool Architecture