AI-Driven Optimization of Hardware Overlay Configurations
Rasha Karakchi
TL;DR
This work tackles the costly trial-and-error process of configuring FPGA overlays by applying Random Forest regression to historical NAPOLY+ design data on a ZCU104 board. The approach predicts resource feasibility and usage before hardware compilation, enabling designers to prune unlikely configurations and accelerate the design cycle. The study demonstrates that predictions closely match actual logical resources and registers, with some underestimation of memory and slight overestimation of fanout, offering a practical path toward AI-assisted FPGA overlay optimization. The authors plan to broaden the framework to additional overlays and boards, moving toward predicting feasible configurations rather than solely resource estimates, with potential for substantial time savings in FPGA development.
Abstract
Designing and optimizing FPGA overlays is a complex and time-consuming process, often requiring multiple trial-and-error iterations to determine a suitable configuration. This paper presents an AI-driven approach to optimizing FPGA overlay configurations, specifically focusing on the NAPOLY+ automata processor implemented on the ZCU104 FPGA. By leveraging machine learning techniques, particularly Random Forest regression, we predict the feasibility and efficiency of different configurations before hardware compilation. Our method significantly reduces the number of required iterations by estimating resource utilization, including logical elements, distributed memory, and fanout, based on historical design data. Experimental results demonstrate that our model achieves high prediction accuracy, closely matching actual resource usage while accelerating the design process.