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Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs

X. Wang, D. Stroobandt

TL;DR

This paper investigates how packing density reshapes FPGA interconnect structure and routability after packing. It introduces RDensity, a Rent’s Rule–based metric, to quantify post-packing density by linking CLB size to terminal counts via $T = t \cdot B^{r}$. Through Rent plots and separate inter-CLB and intra-CLB exponents, the study analyzes how different packing strategies affect interconnect complexity and routability, comparing VTR8 and VTR7 with the AAPack tool. The results show that achieving a balanced RDensity improves routability and reduces routing penalties, highlighting the need for interconnect-aware packing and co-design of packing algorithms with FPGA architectures for better efficiency.

Abstract

Packing is a crucial step of FPGA design, directly impacting interconnect complexity, routing congestion, and overall performance. This paper presents a post-packing interconnect-aware analysis, illustrating how dense (sparse) packing changes the interconnection structure. We introduce a new metric, RDensity, to define post-packing density and investigate its influence on routability. Through a comparative study of two packing tools, we demonstrate that density directly impacts routability. Our findings provide valuable insights into how packing decisions affect FPGA efficiency and offer guidance for improving FPGA packing tools and architecture design by integrating interconnect-aware methods. The goal is to achieve efficient routing while maintaining an optimal balance between cluster density, CLB pin counts, and logical block sizes.

Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs

TL;DR

This paper investigates how packing density reshapes FPGA interconnect structure and routability after packing. It introduces RDensity, a Rent’s Rule–based metric, to quantify post-packing density by linking CLB size to terminal counts via . Through Rent plots and separate inter-CLB and intra-CLB exponents, the study analyzes how different packing strategies affect interconnect complexity and routability, comparing VTR8 and VTR7 with the AAPack tool. The results show that achieving a balanced RDensity improves routability and reduces routing penalties, highlighting the need for interconnect-aware packing and co-design of packing algorithms with FPGA architectures for better efficiency.

Abstract

Packing is a crucial step of FPGA design, directly impacting interconnect complexity, routing congestion, and overall performance. This paper presents a post-packing interconnect-aware analysis, illustrating how dense (sparse) packing changes the interconnection structure. We introduce a new metric, RDensity, to define post-packing density and investigate its influence on routability. Through a comparative study of two packing tools, we demonstrate that density directly impacts routability. Our findings provide valuable insights into how packing decisions affect FPGA efficiency and offer guidance for improving FPGA packing tools and architecture design by integrating interconnect-aware methods. The goal is to achieve efficient routing while maintaining an optimal balance between cluster density, CLB pin counts, and logical block sizes.

Paper Structure

This paper contains 14 sections, 4 equations, 4 figures, 1 table.

Table of Contents

  1. Introduction
  2. Background and Theoretical Framework
  3. Rent's Rule
  4. Post-Packing Interconnection Complexity
  5. Definition of Packing Density
  6. Definition of Rent Packing Density (RDensity)
  7. Methodology
  8. Rent Plot
  9. Post-Packing Analysis
  10. Results and Discussion
  11. Impact of Packing RDensity
  12. Impact of Inter- (Intra-) Rent Exponent
  13. Insights for Architecture
  14. Conclusion and Future Work

Figures (4)

  • Figure 1: Packing process: pre-packing netlist (left) and post-packing netlist (right).
  • Figure 2: Rent's Rule diagram illustrating RDense and RSparse packing; A demonstration of interconnect complexity.
  • Figure 3: Visualization of Rent's rule (pre-packing and post-packing).
  • Figure 4: Comparison of the $D_R$ parameter between VTR 8 (blue) and VTR 7 (red) across different benchmarks.