A 2-6 GHz Ultra-Wideband CMOS Transceiver for Radar Applications
Alin Thomas Tharakan, Prince Philip, Gokulan T., Sumit Kumar, Gaurab Banerjee
TL;DR
This work demonstrates a 65 nm CMOS radar-on-a-chip transceiver delivering full ultra-wideband operation from $2$ to $\!$ $6\,\mathrm{GHz}$ with low power (~$50\ \mathrm{mW}$) and high integration. It combines a Gaussian-pulse transmitter front-end (DCO with a capacitor bank and varactor tuning) and a robust receiver front-end using a cascode LNA with Chebyshev input matching, plus a Gilbert-cell up-conversion mixer, all validated through Cadence-based implementation and measurements. Key contributions include a DCO design methodology to mitigate parasitic capacitances, high-fidelity Gaussian pulse shaping to meet FCC mask limits, and wideband LNA input matching achieving low NF and stable gain across the band. The results indicate a competitive SoC solution for low-power UWB radar sensing, with applications in through-wall detection and biomedical sensing due to the compact, low-cost integration and favorable RF performance.
Abstract
This paper presents a low power, low cost transceiver architecture to implement radar-on-a-chip. The transceiver comprises of a full ultra-wideband (UWB) transmitter and a full UWB band receiver. A design methodology to maximize the tuning range of the voltage-controlled oscillator (VCO) is presented. At the transmitter side, a sub-harmonic mixer is used for signal up-conversion. The receiver low noise amplifier (LNA) has a 2 to 6 GHz input matching bandwidth with a power gain of 9 dB and a noise figure of 2.5 dB. The transceiver is implemented in Cadence EDA tools using 65nm CMOS technology. The system achieves a total dc power consumption of 50 mW. Good noise figure performance; good wide-band matching; gain; high level of integration; low power; low cost of the proposed UWB radar transceiver front-end make it a highly competitive SoC solution for low power UWB transceivers.