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Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing

Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi

TL;DR

Maestro, a RISC-V SoC with unified Vector-Tensor Unit (VTU) and memory-coupled Fast Fourier Transform (FFT) accelerators targeting edge processing for wearable ultrasound devices, fabricated using low-cost TSMC 65nm CMOS technology achieves a $5\times speedup while consuming only 12mW, with an energy consumption of 2mJ in a wearable US channel preprocessing and ML-based postprocessing pipeline.

Abstract

Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumption, and privacy concerns. We present Maestro, a RISC-V SoC with unified Vector-Tensor Unit (VTU) and memory-coupled Fast Fourier Transform (FFT) accelerators targeting edge processing for wearable ultrasound devices, fabricated using low-cost TSMC 65nm CMOS technology. The VTU achieves peak 302GFLOPS/W and 19.8GFLOPS at FP16, while the multi-precision 16/32-bit floating-point FFT accelerator delivers peak 60.6GFLOPS/W and 3.6GFLOPS at FP16, We evaluate Maestro on a US-based gesture recognition task, achieving 1.62GFLOPS in signal processing at 26.68GFLOPS/W, and 19.52GFLOPS in Convolutional Neural Network (CNN) workloads at 298.03GFLOPS/W. Compared to a state-of-the-art SoC with a similar mission profile, Maestro achieves a 5x speedup while consuming only 12mW, with an energy consumption of 2.5mJ in a wearable US channel preprocessing and ML-based postprocessing pipeline.

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing

TL;DR

Maestro, a RISC-V SoC with unified Vector-Tensor Unit (VTU) and memory-coupled Fast Fourier Transform (FFT) accelerators targeting edge processing for wearable ultrasound devices, fabricated using low-cost TSMC 65nm CMOS technology achieves a $5\times speedup while consuming only 12mW, with an energy consumption of 2mJ in a wearable US channel preprocessing and ML-based postprocessing pipeline.

Abstract

Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumption, and privacy concerns. We present Maestro, a RISC-V SoC with unified Vector-Tensor Unit (VTU) and memory-coupled Fast Fourier Transform (FFT) accelerators targeting edge processing for wearable ultrasound devices, fabricated using low-cost TSMC 65nm CMOS technology. The VTU achieves peak 302GFLOPS/W and 19.8GFLOPS at FP16, while the multi-precision 16/32-bit floating-point FFT accelerator delivers peak 60.6GFLOPS/W and 3.6GFLOPS at FP16, We evaluate Maestro on a US-based gesture recognition task, achieving 1.62GFLOPS in signal processing at 26.68GFLOPS/W, and 19.52GFLOPS in Convolutional Neural Network (CNN) workloads at 298.03GFLOPS/W. Compared to a state-of-the-art SoC with a similar mission profile, Maestro achieves a 5x speedup while consuming only 12mW, with an energy consumption of 2.5mJ in a wearable US channel preprocessing and ML-based postprocessing pipeline.

Paper Structure

This paper contains 26 sections, 3 equations, 12 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Vector Cores
  4. Tensor Cores
  5. FFT Accelerators
  6. Wearable Ultrasound Applications and Systems
  7. Maestro Architecture
  8. Host Domain
  9. Cluster Domain
  10. Unified Vector-Tensor Unit
  11. Vector-Tensor Unit Architecture
  12. Buffer Reduction
  13. VAU and VTU Execution Flow
  14. Mixed precision FFT accelerator
  15. MP-FFT Architecture
  16. ...and 11 more sections

Figures (12)

  • Figure 1: Maestro architecture with Host and Cluster domains. The Host domain includes a 32-bit RISC-V core, 64 KiB L2 memory, and two FLLs. The Cluster domain features a 32-bit RISC-V core, 128 KiB L1 memory, DMA, Vector Unit (VTU, VAU, VSLDU, VLSU, VRF), and MP-FFT accelerator, all sharing the L1 memory.
  • Figure 2: Vector-Tensor Unit (VTU) architecture and Vector Register File (VRF) interconnect with Vector Functional Units (VFU). The VTU features the transfer unit and X, W, and Z/W buffers filling the 4$\times$12 Computing Elements (CEs) datapath. The Tensor Control Status Register (TCSR) manages Vector-Tensor capabilities.
  • Figure 3: Vector Arithmetic Unit (VAU) and Vector-Tensor Unit (VTU) temporal execution flow of a general matrix-matrix multiplication (A-B). Vector Register File (VRF) data organization when executing on VTU (C).
  • Figure 4: Multi-Precision FFT Accelerator featuring the Streamer, Controller, Gather and Scatter units, along with two Butterfly Engines: one C32 and one C64.
  • Figure 5: Floating-Point Radix-2 Butterfly Engine.
  • ...and 7 more figures