SSR: A Swapping-Sweeping-and-Rewriting Optimizer for Quantum Circuit Transformation

TL;DR

This work tackles the depth inflation inherent in quantum circuit transformation (QCT) due to hardware connectivity constraints on NISQ devices. It introduces SSR, a Swapping-Sweeping-and-Rewriting optimizer that fuses GA-based generalized SWAP-CNOT commutations, sweeping of CNOT subcircuits, and SAT-based rewriting guided by an ANN-predicted depth, all while enforcing connectivity via an augmented CNF encoding. The method achieves substantial depth reductions across multiple architectures and QCT methods, with improvements up to $29.4\%$ on Grid 5×4 and $16.69\%$ on average, and demonstrates scalability with near-linear runtime growth as qubit count increases. Ablation studies show the complementary benefits of gate-position constraining, GA-driven commutations, and ANN-assisted SAT invocation, and SSR consistently outperforms existing post-QCT optimizers such as CBIR and LR-Synth. These results suggest SSR’s practical impact in improving fidelity and success rates of quantum computations on near-term devices.

Abstract

Quantum circuit transformation (QCT), necessary for adapting any quantum circuit to the qubit connectivity constraints of the NISQ device, often introduces numerous additional SWAP gates into the original circuit, increasing the circuit depth and thus reducing the success rate of computation. To minimize the depth of QCT circuits, we propose a Swapping-Sweeping-and-Rewriting optimizer. This optimizer rearranges the circuit based on generalized gate commutation rules via a genetic algorithm, extracts subcircuits consisting of CNOT gates using a circuit sweeping technique, and rewrites each subcircuit with a functionally equivalent and depth-optimal circuit generated by an SAT solver. The devised optimizer effectively captures the intrinsic patterns of the QCT circuits, and the experimental results demonstrate that our algorithm can significantly reduce the depth of QCT circuits, 26.68\% at most and 12.18\% on average, across all benchmark circuits.

Figures (13)

• Figure 1: SWAP gate decomposition
• Figure 2: Architecture graph of Google Sycamore
• Figure 3: Quantum circuit transformation and depth-optimized rewriting. The AG is linear nearest neighbor and $q_i$ is mapped to physical qubit $v_i$.
• Figure 4: Matrix representation of CNOT circuit
• Figure 5: The flowchart of SSR, the dotted box represents the whole procedure of subcircuits sweeping.