Fast Jet Tagging with MLP-Mixers on FPGAs
Chang Sun, Jennifer Ngadiuba, Maurizio Pierini, Maria Spiropulu
TL;DR
The paper tackles real-time jet tagging at the L1 trigger level under HL-LHC constraints by deploying MLP-Mixer architectures on FPGAs. It combines High Granularity Quantization and Distributed Arithmetic within the hls4ml/Vitis HLS workflow to produce bit-accurate, resource-efficient firmware, achieving state-of-the-art accuracy on a realistic jet dataset while dramatically reducing hardware usage and latency. The results show MLP-Mixer models outperform prior architectures in accuracy and efficiency, with substantial gains in throughput and latency and the ability to prioritize informative features through heterogeneous bitwidths. This work demonstrates the practicality of deploying advanced ML for real-time data processing at particle colliders and outlines avenues for further hardware-aware optimizations.
Abstract
We explore the innovative use of MLP-Mixer models for real-time jet tagging and establish their feasibility on resource-constrained hardware like FPGAs. MLP-Mixers excel in processing sequences of jet constituents, achieving state-of-the-art performance on datasets mimicking Large Hadron Collider conditions. By using advanced optimization techniques such as High-Granularity Quantization and Distributed Arithmetic, we achieve unprecedented efficiency. These models match or surpass the accuracy of previous architectures, reduce hardware resource usage by up to 97%, double the throughput, and half the latency. Additionally, non-permutation-invariant architectures enable smart feature prioritization and efficient FPGA deployment, setting a new benchmark for machine learning in real-time data processing at particle colliders.
