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Scaling IP Lookup to Large Databases using the CRAM Lens

Robert Chang, Pradeep Dogga, Andy Fingerhut, Victor Rios, George Varghese

TL;DR

This work tackles the scalability of IP lookup on modern network processors by introducing the CRAM Lens, an abstract CAM+RAM model that enables rapid estimation of algorithm scalability and guides optimization. It presents three scalable IP lookup algorithms—RESAIL (IPv4), BSIC (IPv6), and MashUp—each deriving from eight CRAM optimization idioms and tailored to RMT/dRMT architectures like Intel Tofino-2. The authors show that RESAIL and BSIC offer substantial improvements over state-of-the-art approaches, achieving up to about 9× lower TCAM usage and 3–4× SRAM reductions, enabling prefix databases an order of magnitude larger than current routing tables. The CRAM model’s predictive accuracy is validated against ideal RMT and ToFino-2 implementations, underscoring its practical value for rapid design-space exploration and mapping of CAM+RAM resources to real hardware.

Abstract

Wide-area scaling trends require new approaches to Internet Protocol (IP) lookup, enabled by modern networking chips such as Intel Tofino, AMD Pensando, and Nvidia BlueField, which provide substantial ternary content-addressable memory (TCAM) and static random-access memory (SRAM). However, designing and evaluating scalable algorithms for these chips is challenging due to hardware-level constraints. To address this, we introduce the CRAM (CAM+RAM) lens, a framework that combines a formal model for evaluating algorithms on modern network processors with a set of optimization idioms. We demonstrate the effectiveness of CRAM by designing and evaluating three new IP lookup schemes: RESAIL, BSIC, and MashUp. RESAIL enables Tofino-2 to scale to 2.25 million IPv4 prefixes$\unicode{x2014}$likely sufficient for the next decade$\unicode{x2014}$while a pure TCAM approach supports only 250k prefixes, just 27% of the current global IPv4 routing table. Similarly, BSIC scales to 390k IPv6 prefixes on Tofino-2, supporting 3.2 times as many prefixes as a pure TCAM implementation. In contrast, existing state-of-the-art algorithms, SAIL for IPv4 and Hi-BST for IPv6, scale to considerably smaller sizes on Tofino-2.

Scaling IP Lookup to Large Databases using the CRAM Lens

TL;DR

This work tackles the scalability of IP lookup on modern network processors by introducing the CRAM Lens, an abstract CAM+RAM model that enables rapid estimation of algorithm scalability and guides optimization. It presents three scalable IP lookup algorithms—RESAIL (IPv4), BSIC (IPv6), and MashUp—each deriving from eight CRAM optimization idioms and tailored to RMT/dRMT architectures like Intel Tofino-2. The authors show that RESAIL and BSIC offer substantial improvements over state-of-the-art approaches, achieving up to about 9× lower TCAM usage and 3–4× SRAM reductions, enabling prefix databases an order of magnitude larger than current routing tables. The CRAM model’s predictive accuracy is validated against ideal RMT and ToFino-2 implementations, underscoring its practical value for rapid design-space exploration and mapping of CAM+RAM resources to real hardware.

Abstract

Wide-area scaling trends require new approaches to Internet Protocol (IP) lookup, enabled by modern networking chips such as Intel Tofino, AMD Pensando, and Nvidia BlueField, which provide substantial ternary content-addressable memory (TCAM) and static random-access memory (SRAM). However, designing and evaluating scalable algorithms for these chips is challenging due to hardware-level constraints. To address this, we introduce the CRAM (CAM+RAM) lens, a framework that combines a formal model for evaluating algorithms on modern network processors with a set of optimization idioms. We demonstrate the effectiveness of CRAM by designing and evaluating three new IP lookup schemes: RESAIL, BSIC, and MashUp. RESAIL enables Tofino-2 to scale to 2.25 million IPv4 prefixeslikely sufficient for the next decadewhile a pure TCAM approach supports only 250k prefixes, just 27% of the current global IPv4 routing table. Similarly, BSIC scales to 390k IPv6 prefixes on Tofino-2, supporting 3.2 times as many prefixes as a pure TCAM implementation. In contrast, existing state-of-the-art algorithms, SAIL for IPv4 and Hi-BST for IPv6, scale to considerably smaller sizes on Tofino-2.

Paper Structure

This paper contains 44 sections, 13 figures, 13 tables, 3 algorithms.

Table of Contents

  1. Introduction
  2. The CRAM Lens
  3. The CRAM Model
  4. Optimization Idioms
  5. Idioms in Action
  6. CRAM for other Hardware Architectures
  7. CRAM for broader Network Applications
  8. Other Algorithmic Requirements
  9. RESAIL
  10. Applying the Optimization Idioms
  11. Building the Data Structures
  12. Performing Lookups
  13. BSIC
  14. Applying the Optimization Idioms
  15. Building the Data Structures
  16. ...and 29 more sections

Figures (13)

  • Figure 1: BGP routing table size over the past two decades
  • Figure 2: From SAIL to RESAIL via CRAM idioms
  • Figure 3: From DXR to BSIC via CRAM idioms
  • Figure 4: From multibit tries to MashUp via CRAM idioms
  • Figure 5: SAIL vs RESAIL for IPv4 prefixes in AS65000
  • ...and 8 more figures