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Real-Time Burst-Mode Digital Signal Processing for Passive Optical Networks

Ji Zhou, Kainan Wu, Haide Wang, Jinyang Yang, Weiping Liu, Junwen Zhang, Changyuan Yu, Xiangjun Xin, Liangchuan Li

TL;DR

The paper tackles the challenge of real-time burst-mode DSP for upstream bursts in a $50\mathrm{G}$ PON by implementing a real-time BM-DSP for $25\mathrm{Gbit/s}$ OOK. It introduces a designed three-part preamble enabling rapid frame detection, SPO estimation, and BM-FDE initialization, and develops BM-FDTR and BM-FDE modules with optimized FFT, MMSE, and DD-LMS implementations to reduce FPGA resource usage by $28.57\%$. The approach achieves real-time operation on a practical FPGA platform and demonstrates BER performance within the $20\%$ FEC limit after transmission over $20$–$40\ \mathrm{km}$ SSMF, with a usable optical budget around $32\ \mathrm{dB}$ at $40$ km. These results provide guidance for BM-DSP ASIC/FPGA design toward scalable $50\mathrm{G}$ PON deployment, highlighting the role of preamble-driven initialization and interpolation-based adaptations to manage complexity.

Abstract

Driven by the ever-increasing capacity demands, the 50G passive optical network (PON) is maturing gradually. One of the main challenges for the 50G PON is implementing burst-mode digital signal processing (BM-DSP) for the burst upstream signal. In this paper, we demonstrate a real-time BM-DSP for burst reception of 25Gbit/s on-off keying signal to meet the asymmetric-mode 50G PON demand. The real-time BM-DSP includes the BM frequency-domain timing recovery and BM frequency-domain equalizer, which can be fast converged based on the 42ns designed preamble. Meanwhile, the simplified implementations for fast-Fourier-transform, minimum-mean-square-error, and decision-directed least-mean-square-error algorithms decrease the DSP resources by 28.57%, enabling the loading of real-time BM-DSP in the field programmable gate array with the limited DSP resources. The real-time implementation of BM-DSP can guide the design of application-specific integrated circuits for 50G PON.

Real-Time Burst-Mode Digital Signal Processing for Passive Optical Networks

TL;DR

The paper tackles the challenge of real-time burst-mode DSP for upstream bursts in a PON by implementing a real-time BM-DSP for OOK. It introduces a designed three-part preamble enabling rapid frame detection, SPO estimation, and BM-FDE initialization, and develops BM-FDTR and BM-FDE modules with optimized FFT, MMSE, and DD-LMS implementations to reduce FPGA resource usage by . The approach achieves real-time operation on a practical FPGA platform and demonstrates BER performance within the FEC limit after transmission over – SSMF, with a usable optical budget around at km. These results provide guidance for BM-DSP ASIC/FPGA design toward scalable PON deployment, highlighting the role of preamble-driven initialization and interpolation-based adaptations to manage complexity.

Abstract

Driven by the ever-increasing capacity demands, the 50G passive optical network (PON) is maturing gradually. One of the main challenges for the 50G PON is implementing burst-mode digital signal processing (BM-DSP) for the burst upstream signal. In this paper, we demonstrate a real-time BM-DSP for burst reception of 25Gbit/s on-off keying signal to meet the asymmetric-mode 50G PON demand. The real-time BM-DSP includes the BM frequency-domain timing recovery and BM frequency-domain equalizer, which can be fast converged based on the 42ns designed preamble. Meanwhile, the simplified implementations for fast-Fourier-transform, minimum-mean-square-error, and decision-directed least-mean-square-error algorithms decrease the DSP resources by 28.57%, enabling the loading of real-time BM-DSP in the field programmable gate array with the limited DSP resources. The real-time implementation of BM-DSP can guide the design of application-specific integrated circuits for 50G PON.

Paper Structure

This paper contains 9 sections, 8 equations, 10 figures, 1 table.

Table of Contents

  1. Introduction
  2. Implementation of Real-Time BM-DSP
  3. Frame Structure and BM-DSP Flow
  4. Real-Time Frame Detection and BM-FDTR
  5. Real-Time Frame Synchronization
  6. Real-Time BM-FDE
  7. Real-Time 128/144-point FFT
  8. Experimental setup and results
  9. CONCLUSION

Figures (10)

  • Figure 1: (a) The frame structure for burst reception of 50G PON. (b) Detailed design of Preamble A and Preamble B. (c) The flow of the real-time signal generation at the transmitter side. (d) The flow of the real-time BM-DSP at the receiver side.
  • Figure 2: The real-time implementation of frame detection and BM-FDTR with SPO estimation based on Preamble A.
  • Figure 3: The real-time implementation of frame synchronization based on Preamble B.
  • Figure 4: The real-time implementation of BM-FDE with feedforward channel estimation based on Preamble C.
  • Figure 5: (a) Real-time implementation of 128-point FFT, (b) Real-time implementation of the radix-2 FFT, (c) Real-time implementation of 144-point FFT, (d) Real-time implementation of the radix-3 FFT.
  • ...and 5 more figures