PVU: Design and Implementation of a Posit Vector Arithmetic Unit (PVU) for Enhanced Floating-Point Computing in Edge and AI Applications
Xinyu Wu, Yaobin Wang, Tianyi Zhao, Jiawei Qin, Zhu Liang, Jie Fu
TL;DR
The paper tackles energy efficiency and precision bottlenecks of IEEE 754 in edge AI workloads by adopting the Posit format and introducing PVU, a vector Posit arithmetic unit implemented in Chisel. PVU supports vector addition, subtraction, multiplication, division, and dot product, and integrates with the RISC-V RVV extension through a custom instruction set, enabling seamless software-hardware co-design. Experimental results show PVU achieving 100% accuracy for most operations (95.84% for division) with a compact hardware footprint of around 65k LUTs and 108 Muxes, demonstrated on FPGA and validated with CNN front-end data and various benchmark datasets. The work delivers an open-source, parameterizable PVU generator and demonstrates PVU’s potential as a scalable, energy-efficient floating-point platform for edge and AI applications.
Abstract
With the rapid development of edge computing, artificial intelligence and other fields, the accuracy and efficiency of floating-point computing have become increasingly crucial. However, the traditional IEEE 754 floating-point system faces bottlenecks in energy consumption and computing accuracy, which have become major constraints. To address this issue, the Posit digital system characterized by adaptive accuracy, broader dynamic range and low hardware consumption has been put forward. Despite its widespread adoption, the existing research mainly concentrates on scalar computation, which is insufficient to meet the requirements of large-scale parallel data processing. This paper proposes, for the first time, a Posit Vector Arithmetic Unit (PVU) designed using the Chisel language. It supports vector operations such as addition, subtraction, multiplication, division, and dot product, thereby overcoming the limitations of traditional scalar designs and integrating the RISC-V instruction extension. The contributions of this paper include the efficient implementation of the vector arithmetic unit, the parametric and modular hardware design as well as the verification of the practical application of the positive digital system. This paper extracts the quantized data of the first convolutional layer for verification. Experiments indicate that the accuracy rate of the division operation is 95.84\%, and the accuracy rate of the remaining operations is 100\%. Moreover, the PVU is implemented with only 65,407 LUTs. Therefore, PVU has great potential as a new-generation floating-point computing platform in various fields.