AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies

TL;DR

AnalogGenie tackles the core challenge of scalable analog IC topology design by introducing a domain-specific GPT-based generator that operates on a pin-level undirected graph represented as an Eulerian circuit. It builds a large, diverse dataset of $3350$ analog circuit topologies and employs data augmentation to expand training sequences by about $70\times$, enabling generation of large, unseen topologies with practical performance metrics. The approach achieves superior correctness, scalability, novelty, and FoM across multiple circuit types compared with state-of-the-art baselines, and demonstrates zero-shot capabilities to design new topologies beyond its training set. This work broadens the applicability of generative AI to analog circuit design, offering a path toward automatic, large-scale IC design and potentially informing future integration with digital design and automated layout and sizing pipelines.

Abstract

The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs. Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, $\textbf{AnalogGenie}$, a $\underline{\textbf{Gen}}$erat$\underline{\textbf{i}}$ve $\underline{\textbf{e}}$ngine for automatic design/discovery of $\underline{\textbf{Analog}}$ circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts. Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available at https://github.com/xz-group/AnalogGenie.

Figures (13)

• Figure 1: Current states of analog circuit topology generation. (a) Typical data representation for analog circuit topology. (b) Existing analog circuit topology generation paradigms. Graph provides a clear one-to-one mapping between the graph generation process and the circuit design process. PySpice code is a high-level representation, making its generation process more prone to error.
• Figure 2: Overview of AnalogGenie. AnalogGenie represents each topology as a sequence and generates all sorts of analog circuit topology from scratch by predicting the device pin to connect.
• Figure 3: Comparison between two different circuit graph representations. (a) An example showing the limitation of device level graph representation used by previous graph generation work dong2023cktgnnlu2023automatic, which oversimplified the analog circuit connection and led to non-unique mapping from graph to circuit topology during generation. (b) Our device pin-level graph representation ensures there is a unique mapping between each graph and circuit topology and is able to explicitly represent every connection in a circuit topology.
• Figure 4: Comparisons between AnalogGenie pretrained with unaugmented data and augmented data. Our augmentation method is able to improve validation loss around 8.5$\times$.
• Figure 5: Our analog circuit dataset's device number distribution.