Digital-Controlled Method of Conveyor-Belt Spin Shuttling in Silicon for Large-Scale Quantum Computation

TL;DR

The paper tackles scalability and fidelity bottlenecks in conveyor-belt spin shuttling for silicon qubits by replacing room-temperature analog control with a digital-controlled scheme that embeds a cryogenic switch matrix and RC filters to synthesize near-sinusoidal waveforms from a few DC voltage levels. This digital approach dramatically reduces wiring overhead while preserving high shuttling fidelity, achieving $F \\gtrsim 0.999$ (≈99.9%) and exhibiting robustness to valley coupling and interface roughness. Heat dissipation estimates suggest the cryogenic power budget remains within typical dilution refrigerator capabilities for large qubit counts (on the order of $10^6$ qubits) using modest voltages and frequencies. The method offers a scalable path toward fault-tolerant silicon-based quantum computing with QEC, and the authors highlight avenues for experimental demonstration and circuit-level optimizations.

Abstract

We propose a digital-controlled conveyor-belt shuttling method for silicon-based quantum processors, addressing the scalability challenges of conventional analog sinusoidal implementations. By placing a switch matrix and low-pass filters in a cryogenic environment, our approach synthesizes near-sinusoidal waveforms from a limited number of DC voltage levels. Simulation results demonstrate that the proposed method achieves fidelity comparable to analog methods while significantly reducing wiring overhead and power dissipation. Moreover, the design offers robustness against device-level variations, enabling large-scale integration of high-fidelity spin shuttling for quantum error correction.

Figures (10)

• Figure 1: Conceptual figures of the analog-controlled approach (left and middle) and the proposed digital-controlled approach (right) for spin qubit shuttling in Si devices. The conventional approach 2022-QuBus2024-QuBus2024-QuBus-EPR2024-QuTech corresponds to the middle figure, where a few (phase-modulated) sinusoidal waveforms are applied periodically to gate electrodes. This method is free from wiring problem at room temperature but requires many fan-out cables and these would causes the amplitude dumping of waveforms due to the impedance mismatch. To mitigate the dumping effect, the larger voltage would be needed. This fan-out problem can be solved by introducing individual control depicted in the left figure, however, it will face wiring problem. Our approach depicted the right figure has a potential to solve the dilemma. We generate near (phase-modulated) sinusoidal waveform by placing the waveform-generation functionality (switches and filters) in the dilution refrigerator (Cryo).
• Figure 2: One example of the proposed implementation (see Fig. \ref{['fig-original_vs_proposal']}, right). A switch matrix (SWMX), low-pass filter (LPF), and offset control are placed in the sub-100 mK region of the dilution refrigerator (Cryo). Logic circuits (LOG) at a higher temperature stage control them. At room temperature, only $N_{\mathrm{DC}}$ DC voltage sources plus one additional serial control line (and a few other lines) are necessary, independent of $N_{\rm{qubit}}$.
• Figure 3: Effect of the time constant ($\tau$) on the voltage waveform in the proposed method. The top panel shows the original sinusoid; the bottom panels show resulting waveforms for $\tau/t_0=0.01,0.1,1.0$.
• Figure 4: Numerical results for the proposed digital shuttling . In the top left panels, we show the schematic picture of the device we considered. Multiple gate electrodes are arranged along the shuttling direction (the $x$-axis) with a uniform spacing $l$. Each gate covers an area of ($W_x\times W_y$) and is positioned above the silicon layer at a distance $h$. In the bottom left, the applied gate voltages is shown. In our analysis, we set $W_x=W_y=30\,\mathrm{nm}, l=1\,\mathrm{nm}, h=10\,\mathrm{nm}, N=3, V_0=200\,\mathrm{mV}, 1/f=30\,\mathrm{ns}$, $E_{v,0}=200\,\mu\hbox{eV}$ and $\theta=0.3^\circ$. The right plots show the time evolution of the quantum dot position $x_{\rm{QD}}$, the shuttling velocity $v_{\rm{s}}$, the quantum dot size $a_x$, and the leakage error $1-\mathcal{F}$.
• Figure 5: Numerical results comparing shuttling performance for various $\tau$ values to the original (sinusoidal) method. We fix $t_0=30\,\mathrm{ns}$, $W=30\,\mathrm{nm}$, $l=1\,\mathrm{nm}$, $N=3$, and consider $V_0=200\,\mathrm{mV}$ (top panel) and $V_0=300\,\mathrm{mV}$ (bottom panel). The leftmost columns are the original sinusoidal method, while the others are the proposed digital approach with $\tau/t_0=0.01,0.1,0.2,0.5$. For each case, we show $x_{\rm{QD}}$, $v_{\mathrm s}$, $a_x$, and $1-\mathcal{F}$.