High-Fidelity Integrated Quantum Photonic Logic Via Robust Directional Couplers

TL;DR

This work presents a passive, geometry-based strategy to suppress first-order sensitivity of directional couplers to fabrication variations in integrated quantum photonics. By identifying and operating at a stationary point W_stat where ∂κ/∂W ≈ 0, the authors demonstrate a robust two-photon CNOT gate on a silicon-on-insulator chip that outperforms a non-robust reference by reducing gate error without active tuning or added footprint. The robust device achieves a mean fidelity near 93.30%, approaching the source-limited ceiling set by photon indistinguishability, and Monte Carlo simulations corroborate the suppression of first-order errors. Additionally, simulations indicate substantial improvements in entangled-state generation for one-way quantum computing, highlighting passive geometric error mitigation as a scalable, platform-agnostic approach to high-fidelity photonic quantum computing.

Abstract

Scalable quantum information processing with integrated photonics requires quantum logic operations with high fidelity and robustness. Directional couplers, the fundamental elements enabling quantum interference and logic operations, are inherently sensitive to fabrication imperfections and environmental fluctuations, leading to reduced gate fidelities. Here, we experimentally demonstrate a passive design strategy that mitigates these errors by exploiting a stationary geometrical configuration in uniform directional couplers, where first-order variations in the coupling coefficient are intrinsically suppressed. The robust geometry is implemented in a silicon-on-insulator photonic chip hosting two-photon controlled-NOT (CNOT) quantum gates and its performance is directly compared to a non-optimized design. Measurements indicate a mean gate fidelity of $93.30 \pm 0.11\%$, representing a clear improvement over the non-robust implementation mean fidelity of $91.93 \pm 0.17\%$, without any active tuning or footprint increase. This performance approaches the theoretical limit of $93.78\%$, imposed by the imperfect source. Monte Carlo simulations incorporating realistic fabrication noise confirm the observed enhancement and reveal consistent suppression of gate-level error rates. These results demonstrate a compact, fabrication-tolerant building block for scalable, fault-tolerant photonic quantum circuits and highlight the power of passive geometric error mitigation in quantum hardware design.

Figures (4)

• Figure 1: Schematic of the stationary-geometry coupler principle. (a) A schematic drawing of a directional coupler. (b-d) Two-dimensional cross section of the interaction region in a directional coupler, showing three cases. (b) The waveguide widths are wider then the stationary point, resulting in larger coupling coefficient due to large overlap area. (c) Waveguide widths are exactly at the stationary point. (d) The waveguides are narrower than the stationary width, causing a larger coupling coefficient due to stronger evanescent field. (e) The coupling coefficient $\kappa$ is minimized at the stationary width $W_\mathrm{stat}$ as seen from both measurements (brown data points) and numerical simulations (blue solid line). The blue shaded area shows the coupling coefficient variation in the simulation due to a 5nm width variation.(f) The dual-rail CNOT circuit used in this work.
• Figure 2: The effect of the refractive index and geometry on the stationary point. The existence of such a stationary point is universal across integrated platforms and wavelengths, though its location depends on the (a) refractive-index contrast and (b-c) specific geometry.
• Figure 3: Truth table reconstruction of the CNOT gate. a The Hong-Ou-Mandel interference profile of the CNOT gate. The visibility was extracted by fitting a Gaussian function (orange) to the HOM interference profile (blue), and was reported as 95.7%. b The mean error probability as a function of the design width. The blue curve shows the error probability as a function of the design width as obtained from Monte Carlo simulations. The experimental results are shown as green points, and show even better improvement than the theoretical predictions. The HOM limit was calculated to be 6.22% and is shown as a black dashed line. c The truth table reconstruction of the CNOT gate for the reference device. It shows a mean error probability of 8.07% ± 0.17%. d The truth table reconstruction of the CNOT gate for the robust design. It shows a mean error probability of 6.70% ± 0.11%.
• Figure 4: The effect of stationary-geometry couplers on the resource generation for one-way quantum computing. (a) The Type-II fusion gate in its well known free space implementation, which consists of a single polarizing beam splitter (PBS) and four half-wave plates (HWP) rotated at a 45 degree angle. (b) The equivalent integrated dual-rail circuit, which consists of four directional couplers with a reflectivity of 1/2 and a single waveguide crossing. (c) The robust design (orange) achieves a mean entanglement entropy loss of 0.49 × $10^{-4}$, as opposed to the entropy loss of the arbitrary design (blue) of 2.19 × $10^{-4}$. This demonstrates the possible usage of stationary-geometry couplers in highly entangled state generation.