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A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications

Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gurkaynak, Davide Rossi, Luca Benini

TL;DR

This work tackles the challenge of executing mixed-critical AI workloads with strict time-predictability under tight power envelopes on edge devices. It proposes a 16nm heterogeneous SoC with hardware IPs for resource partitioning, a FP8-capable vector cluster, and a 12-core mission-critical accelerator, integrated across three Clock domains to enable end-to-end determinism and efficient virtualization. Experimental results show strong energy efficiency and throughput within a $1.2\ \mathrm{W}$ envelope, along with interference-aware mechanisms that preserve performance under shared resource contention. The authors demonstrate hardware-based time predictability, rapid fault recovery, and competitive performance versus state-of-the-art edge and mixed-criticality solutions, with open-source HDL for reproducibility. Overall, the design provides a practical path to reliable, deterministic AI processing at the edge for automotive, robotics, and space applications.

Abstract

Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges, in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm2.

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications

TL;DR

This work tackles the challenge of executing mixed-critical AI workloads with strict time-predictability under tight power envelopes on edge devices. It proposes a 16nm heterogeneous SoC with hardware IPs for resource partitioning, a FP8-capable vector cluster, and a 12-core mission-critical accelerator, integrated across three Clock domains to enable end-to-end determinism and efficient virtualization. Experimental results show strong energy efficiency and throughput within a envelope, along with interference-aware mechanisms that preserve performance under shared resource contention. The authors demonstrate hardware-based time predictability, rapid fault recovery, and competitive performance versus state-of-the-art edge and mixed-criticality solutions, with open-source HDL for reproducibility. Overall, the design provides a practical path to reliable, deterministic AI processing at the edge for automotive, robotics, and space applications.

Abstract

Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges, in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm2.

Paper Structure

This paper contains 12 sections, 8 figures.

Table of Contents

  1. Introduction
  2. SoC Architecture
  3. Hardware IPs For Time-Predictability
  4. Compact, Efficient, Vector Cluster
  5. Cluster for Mission-Critical
  6. Evaluation and Measurements
  7. Performance vs Energy Efficiency
  8. Interference-aware execution
  9. Comparison with State-of-the-Art
  10. Comparison with Mixed-Criticality SoCs
  11. Comparison with edge and Vector Processors
  12. Conclusion

Figures (8)

  • Figure 1: SoC Architecture.
  • Figure 2: Architectures of the hardware IPs for predictability: a) ; b) ; c) .
  • Figure 3: a) Hardware fast recovery (HFR) mechanisms for dual-lockstep mode (DLM) case. b) HFR Finite State Machine. c) performance.
  • Figure 4: a) SoC micro-graph; b) testing setup.
  • Figure 5: Voltage/Frequency/Power and Performance/Energy Efficiency sweeps of (a, b) and vector (c, d) clusters.
  • ...and 3 more figures