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AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs

Vojtech Mrazek, Zdenek Vasicek

TL;DR

The paper tackles energy-efficient median filtering by introducing a formal, BDD-based framework to quantify and guarantee the quality of approximate medians via rank-error metrics. It combines this with Cartesian Genetic Programming to perform a two-stage, hardware-aware search that reduces CAS elements while controlling the error distribution, using a precise cost model for fully pipelined implementations. Key contributions include a scalable, data-independent evaluation of worst-case and distributional errors, an explicit quality metric tied to the error histogram, and a hardware-cost estimation method that supports automated synthesis. Empirically, the approach achieves substantial area and power reductions (e.g., ~30% area, ~36% power in a representative example) while maintaining acceptable image-quality metrics (SSIM) for typical multimedia tasks, and demonstrates scalable, faster-than-exhaustive analysis via BDDs.

Abstract

The increasing demand for energy-efficient solutions has led to the emergence of an approximate computing paradigm that enables power-efficient implementations in various application areas such as image and data processing. The median filter, widely used in image processing and computer vision, is of immense importance in these domains. We propose a systematic design methodology for the design of power-efficient median networks suitable for on-chip or FPGA-based implementations. A search-based design method is used to obtain approximate medians that show the desired trade-offs between accuracy, power consumption and area on chip. A new metric tailored to this problem is proposed to quantify the accuracy of approximate medians. Instead of the simple error rate, our method analyses the rank error. A significant improvement in implementation cost is achieved. For example, compared to the well-optimized high-throughput implementation of the exact 9-input median, a 30\% reduction in area and a 36\% reduction in power consumption was achieved by introducing an error by one position (i.e., allowing the 4th or 6th lowest input to be returned instead of the median).

AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs

TL;DR

The paper tackles energy-efficient median filtering by introducing a formal, BDD-based framework to quantify and guarantee the quality of approximate medians via rank-error metrics. It combines this with Cartesian Genetic Programming to perform a two-stage, hardware-aware search that reduces CAS elements while controlling the error distribution, using a precise cost model for fully pipelined implementations. Key contributions include a scalable, data-independent evaluation of worst-case and distributional errors, an explicit quality metric tied to the error histogram, and a hardware-cost estimation method that supports automated synthesis. Empirically, the approach achieves substantial area and power reductions (e.g., ~30% area, ~36% power in a representative example) while maintaining acceptable image-quality metrics (SSIM) for typical multimedia tasks, and demonstrates scalable, faster-than-exhaustive analysis via BDDs.

Abstract

The increasing demand for energy-efficient solutions has led to the emergence of an approximate computing paradigm that enables power-efficient implementations in various application areas such as image and data processing. The median filter, widely used in image processing and computer vision, is of immense importance in these domains. We propose a systematic design methodology for the design of power-efficient median networks suitable for on-chip or FPGA-based implementations. A search-based design method is used to obtain approximate medians that show the desired trade-offs between accuracy, power consumption and area on chip. A new metric tailored to this problem is proposed to quantify the accuracy of approximate medians. Instead of the simple error rate, our method analyses the rank error. A significant improvement in implementation cost is achieved. For example, compared to the well-optimized high-throughput implementation of the exact 9-input median, a 30\% reduction in area and a 36\% reduction in power consumption was achieved by introducing an error by one position (i.e., allowing the 4th or 6th lowest input to be returned instead of the median).

Paper Structure

This paper contains 10 sections, 5 equations, 3 figures, 1 table.

Table of Contents

  1. Introduction
  2. Analyzing Approximate Medians
  3. Worst-Case Error Analysis
  4. Error Distribution Analysis
  5. Analysis using BDDs
  6. Proposed Approximation Method
  7. Results and Discussion
  8. Analysis of Approximate Medians
  9. Designed Circuits
  10. Conclusions

Figures (3)

  • Figure 1: Virtual circuit used for an efficient worst-case and error distribution analysis
  • Figure 2: Example of a comparison network consisting of 7 operations encoded using CGP with parameters: $n=5$, $n_c=8$. This network can be encoded using the sequence $(0,1,0)(2,3,0)(6,7,0)(8,4,0)(5,10,1)$$(12,4,0)(13,15,0)(15,16,1)(17)$.
  • Figure 3: Computational complexity of the proposed BDD-based analysis framework compared to the subset of 1000 vectors in permutations Vasicek2016.