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The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration

Felix Arnold, Maxence Bouvier, Ryan Amaudruz, Renzo Andri, Lukas Cavigelli

TL;DR

The paper addresses the high cost of MIG-based combinational circuit synthesis by introducing predictor-guided random design space exploration that augments a random-search framework with next-state prediction and iterative selection. The architecture comprises prm (predictor), pom (policy) and iism (restart mechanism), leveraging data from uniformly sampled recipes and training multiple predictor models (statistical, MLP, transformer). It demonstrates substantial gains, reporting up to 14x speedup and up to 20.94% MIG minimization on EPFL benchmarks, and analyzes the nuanced role of prediction accuracy versus randomness. The approach is presented as hyperparameter-sensitive yet versatile, with results suggesting robustness to randomness and potential extensions via reinforcement learning and tool-agnostic deployment. Public release of minimized designs further enhances accessibility for open-source EDA research.

Abstract

This work introduces an innovative method for improving combinational digital circuits through random exploration in MIG-based synthesis. High-quality circuits are crucial for performance, power, and cost, making this a critical area of active research. Our approach incorporates next-state prediction and iterative selection, significantly accelerating the synthesis process. This novel method achieves up to 14x synthesis speedup and up to 20.94% better MIG minimization on the EPFL Combinational Benchmark Suite compared to state-of-the-art techniques. We further explore various predictor models and show that increased prediction accuracy does not guarantee an equivalent increase in synthesis quality of results or speedup, observing that randomness remains a desirable factor.

The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration

TL;DR

The paper addresses the high cost of MIG-based combinational circuit synthesis by introducing predictor-guided random design space exploration that augments a random-search framework with next-state prediction and iterative selection. The architecture comprises prm (predictor), pom (policy) and iism (restart mechanism), leveraging data from uniformly sampled recipes and training multiple predictor models (statistical, MLP, transformer). It demonstrates substantial gains, reporting up to 14x speedup and up to 20.94% MIG minimization on EPFL benchmarks, and analyzes the nuanced role of prediction accuracy versus randomness. The approach is presented as hyperparameter-sensitive yet versatile, with results suggesting robustness to randomness and potential extensions via reinforcement learning and tool-agnostic deployment. Public release of minimized designs further enhances accessibility for open-source EDA research.

Abstract

This work introduces an innovative method for improving combinational digital circuits through random exploration in MIG-based synthesis. High-quality circuits are crucial for performance, power, and cost, making this a critical area of active research. Our approach incorporates next-state prediction and iterative selection, significantly accelerating the synthesis process. This novel method achieves up to 14x synthesis speedup and up to 20.94% better MIG minimization on the EPFL Combinational Benchmark Suite compared to state-of-the-art techniques. We further explore various predictor models and show that increased prediction accuracy does not guarantee an equivalent increase in synthesis quality of results or speedup, observing that randomness remains a desirable factor.

Paper Structure

This paper contains 5 sections, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Method
  3. Experiments
  4. Results
  5. Conclusion

Figures (3)

  • Figure 1: Overview of the proposed prediction-based dse framework. (a) Multiple parallel chains and iism. (b) Unitary steps with recipe selection and mt recipe processing. (c) Detailed view of recipe performance prediction and recipe selection by the prm and pom.
  • Figure 2: Effect of the temperature on the speedup factor for various target values for ctrl.v. Statistical model. a) 1SA, b) 2SA.
  • Figure 3: Effect of chain length and number of parallel chains on achieved minimum, mean and median transistor counts.