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The Power of Graph Signal Processing for Chip Placement Acceleration

Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang

TL;DR

The paper addresses the high computational cost of chip placement by proposing GiFt, a parameter-free, Graph Signal Processing–based placement acceleration. GiFt constructs a multi-frequency graph filter to denoise and smooth circuit graphs, producing optimized initial placements that substantially reduce the iteration burden of analytical placers without requiring model training. By showing that classical eigenvector-based and GCN-based placers are special cases of GiFt, the approach unifies prior methods and avoids their training overhead, while achieving competitive or superior results on ISPD2014 benchmarks and real designs. Empirically, integrating GiFt with analytical placers (GiFt-RePlAce, GiFt-DREAMPlace) yields large runtime reductions (e.g., over 45% faster than DREAMPlace) and fewer iterations, enabling fast, scalable, high-quality chip placement with practical impact for EDA workflows.

Abstract

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%.

The Power of Graph Signal Processing for Chip Placement Acceleration

TL;DR

The paper addresses the high computational cost of chip placement by proposing GiFt, a parameter-free, Graph Signal Processing–based placement acceleration. GiFt constructs a multi-frequency graph filter to denoise and smooth circuit graphs, producing optimized initial placements that substantially reduce the iteration burden of analytical placers without requiring model training. By showing that classical eigenvector-based and GCN-based placers are special cases of GiFt, the approach unifies prior methods and avoids their training overhead, while achieving competitive or superior results on ISPD2014 benchmarks and real designs. Empirically, integrating GiFt with analytical placers (GiFt-RePlAce, GiFt-DREAMPlace) yields large runtime reductions (e.g., over 45% faster than DREAMPlace) and fewer iterations, enabling fast, scalable, high-quality chip placement with practical impact for EDA workflows.

Abstract

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%.

Paper Structure

This paper contains 20 sections, 1 theorem, 20 equations, 3 figures, 2 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Graph Signal Processing
  4. Global Placement
  5. Method
  6. Enhancing Placement from GSP Perspective
  7. GiFt: An Efficient Placement Speedup Technique
  8. The algorithm of GiFt.
  9. The beneficial attributes of GiFt for placement.
  10. The workflow of GiFt-equipped placement process.
  11. Analyzing Existing Placers from GSP Perspective
  12. Eigenvector-based Placer
  13. GCN-based Placer
  14. Experimental Results
  15. Experiment Settings
  16. ...and 5 more sections

Key Result

Theorem 1

The normalized adjacency matrix $\tilde{A}=D^{-\frac{1}{2}}AD^{-\frac{1}{2}}$ is a graph filter corresponding to the filter function $h(\lambda)=1-\lambda$.

Figures (3)

  • Figure 1: The workflow of GiFt-equipped placement process.
  • Figure 2: Eigenvalue distributions of normalized Laplacians with different graph filters: (a) under different self-loops. (b) with $\tilde{A}$ filter at various $k$, (c) with augmented $\tilde{A}$ filter at various $k$.
  • Figure 3: (a) Cell locations produced by GiFt. (b) Density curves during placement.

Theorems & Definitions (1)

  • Theorem 1