Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators

TL;DR

CMSwitch presents a dual‑mode CIM compiler that jointly optimizes compute/memory mode switching, mapping, and scheduling for CIM accelerators. By integrating a dual‑mode conscious hardware abstraction with dynamic programming based network segmentation and mixed‑integer programming based resource allocation, it outputs a meta‑operator flow encoding the mode plan. Empirical results show an average 1.31× speedup over state‑of‑the‑art CIM compilers across CNNs and transformers, with manageable switch overhead and scalable performance for large models that exceed on‑chip memory. This work demonstrates the practical potential of fully exploiting CIM dual‑mode capabilities to adapt hardware resources to diverse DNN workloads.

Abstract

Computing-in-memory (CIM) architectures demonstrate superior performance over traditional architectures. To unleash the potential of CIM accelerators, many compilation methods have been proposed, focusing on application scheduling optimization specific to CIM. However, existing compilation methods often overlook CIM's capability to switch dynamically between compute and memory modes, which is crucial for accommodating the diverse memory and computational needs of real-world deep neural network architectures, especially the emerging large language models. To fill this gap, we introduce CMSwitch, a novel compiler to optimize resource allocation for CIM accelerators with adaptive mode-switching capabilities, thereby enhancing the performance of DNN applications. Specifically, our approach integrates the compute-memory mode switch into the CIM compilation optimization space by introducing a new hardware abstraction attribute. Then, we propose a novel compilation optimization pass that identifies the optimal network segment and the corresponding mode resource allocations using dynamic programming and mixed-integer programming. CMSwitch uses the tailored meta-operator to express the compilation result in a generalized manner. Evaluation results demonstrate that CMSwitch achieves an average speedup of 1.31$\times$ compared to existing SOTA CIM compilation works, highlighting CMSwitch's effectiveness in fully exploiting the potential of CIM processors for a wide range of real-world DNN applications.

Figures (18)

• Figure 1: (a) CIM switching between memory and compute mode by setting up control signals to the input driver; (b) Normalized performance variation with the ratio of arrays in compute mode changes. Please note that putting more CIM arrays in compute mode deprives them of the chance of working as scratchpad memory for storing and loading intermediate data, e.g. activations. CIM arrays in compute mode must store static data, i.e. pre-determined weights.
• Figure 2: Hierarchical CIM architecture (a) CIM core with CIM arrays and the corresponding peripheral units; (b) CIM array and the corresponding peripheral units; (c) CIM array.
• Figure 3: Dual-mode CIM Array.
• Figure 4: (a) Existing typical CIM mapping method that treats all the CIM arrays as compute arrays; (b) Dual-mode-aware mapping method.
• Figure 5: (a)(b) Normalized performance variation with the changes of compute/memory array; (c) Arithmetic Intensity.