A Review of Memory Wall for Neuromorphic Computing

TL;DR

The paper addresses the memory bottlenecks in FPGA-based neuromorphic computing by surveying memory technologies from SRAM/BRAM/URAM, DRAM, and HBM to emerging non-volatile memories such as ReRAM and PCM. It analyzes these options along latency, bandwidth, power, density, and scalability, supported by case studies that demonstrate performance and energy implications. Key findings show that SRAM provides low latency for critical data, DRAM offers higher density with latency trade-offs, and HBM drastically reduces data movement, while emerging memories enable energy-efficient in-memory computation with integration challenges. The work offers practical guidance for researchers and practitioners on selecting and optimizing memory architectures to enhance the performance and energy efficiency of FPGA-based neuromorphic platforms, thereby advancing AI applications.

Abstract

This paper reviews memory technologies used in Field-Programmable Gate Arrays (FPGAs) for neuromorphic computing, a brain-inspired approach transforming artificial intelligence with improved efficiency and performance. It focuses on the essential role of memory in FPGA-based neuromorphic systems, evaluating memory types such as Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), High-Bandwidth Memory (HBM), and emerging non-volatile memories like Resistive RAM (ReRAM) and Phase-Change Memory (PCM). These technologies are analyzed based on latency, bandwidth, power consumption, density, and scalability to assess their suitability for storing and processing neural network models and synaptic weights. The review provides a comparative analysis of their strengths and limitations, supported by case studies illustrating real-world implementations and performance outcomes. This review offers insights to guide researchers and practitioners in selecting and optimizing memory technologies, enhancing the performance and energy efficiency of FPGA-based neuromorphic platforms, and advancing applications in artificial intelligence.

Figures (4)

• Figure 1: Hierarchical Dataflow in Neural Network Accelerator with Layered Memory and Processing Units.
• Figure 2: Dataflow Architecture for Neural Network Processing with FIFO Buffers and Activation Management.
• Figure 3: Neural Network Accelerator Architecture with Processing Elements and High-Bandwidth Memory Integration.
• Figure 4: Neuromorphic Crossbar Architecture with Signal Encoding and Conversion Modules.