EDA-Q: Electronic Design Automation for Superconducting Quantum Chip

TL;DR

This paper addresses the lack of a full-stack EDA framework for superconducting quantum chips and introduces EDA-Q, a five-layer entity–control–process–library architecture that unifies topology design, equivalent circuits, layout, device mapping, routing, fabrication process mapping, and simulation. It implements end-to-end automation via a Generalized Functional Modules Model and a Request Aggregation Mapping Model, with validation through end-to-end design workflows and real chip examples. The results demonstrate reduced design cycles, higher automation, and effective integration with fabrication considerations, highlighting practical impact for rapid, scalable quantum chip development. The authors plan to expand the algorithm and library ecosystems in collaboration with fabrication partners and release the project under GPL-3.0 to foster community growth.

Abstract

Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.

Figures (11)

• Figure 1: The Software Architecture of EDA-Q
• Figure 2: The equivalent circuit of two superconducting qubits directly coupled by capacitance.
• Figure 3: Calculation of the capacitance matrix for the superconducting qubit model.
• Figure 4: Working architecture of device mapper
• Figure 5: The Process of SQCR-Maze Pathfinding Algorithm