Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment

TL;DR

This work tackles learning circuit representations while preserving logical equivalence by introducing a constrained masked modeling paradigm, MGVGA, built from Masked Gate Modeling (MGM) and Verilog-AIG Alignment (VGA). MGM masks gates in the latent space to maintain equivalence, while VGA uses LLM-derived Verilog embeddings to constrain reconstruction and inject abstract circuit function into GNN learning via cross-attention. The method achieves state-of-the-art performance on QoR prediction and logic equivalence identification across logic synthesis benchmarks, and demonstrates strong generalization across different GNN architectures. By combining structural and functional learning with LLM-guided constraints, MGVGA offers a principled approach for robust circuit representation learning applicable to EDA tasks. The authors provide open-source code to facilitate replication and adoption in downstream tooling.

Abstract

Understanding the structure and function of circuits is crucial for electronic design automation (EDA). Circuits can be formulated as And-Inverter graphs (AIGs), enabling efficient implementation of representation learning through graph neural networks (GNNs). Masked modeling paradigms have been proven effective in graph representation learning. However, masking augmentation to original circuits will destroy their logical equivalence, which is unsuitable for circuit representation learning. Moreover, existing masked modeling paradigms often prioritize structural information at the expense of abstract information such as circuit function. To address these limitations, we introduce MGVGA, a novel constrained masked modeling paradigm incorporating masked gate modeling (MGM) and Verilog-AIG alignment (VGA). Specifically, MGM preserves logical equivalence by masking gates in the latent space rather than in the original circuits, subsequently reconstructing the attributes of these masked gates. Meanwhile, large language models (LLMs) have demonstrated an excellent understanding of the Verilog code functionality. Building upon this capability, VGA performs masking operations on original circuits and reconstructs masked gates under the constraints of equivalent Verilog codes, enabling GNNs to learn circuit functions from LLMs. We evaluate MGVGA on various logic synthesis tasks for EDA and show the superior performance of MGVGA compared to previous state-of-the-art methods. Our code is available at https://github.com/wuhy68/MGVGA.

Figures (5)

• Figure 1: Possible reconstruct AIGs for masked AIG. If circuit gates are masked, there are various logic-correct solutions for reconstruction.
• Figure 2: Logic equivalence between Verilog code and AIG. For a circuit design, AIG can be translated from Verilog code.
• Figure 3: Overview of the MGVGA for circuit representation including masked gate modeling and Verilog-AIG alignment. For both MGM and VGA, the AIG reconstruction is implemented by gate type prediction and gate-level degree prediction from reconstructed representation.
• Figure 4: The constraint block for VGA.
• Figure 5: Application of MGVGA in QoR prediction and logic equivalence identification.