Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions

TL;DR

RowHammer remains a critical reliability challenge in DRAM as chips scale. This work provides the first rigorous experimental study of how reducing preventive refresh latency affects RowHammer on 388 real DDR4 chips, showing that latency can be substantially reduced without worsening vulnerability for most devices. Building on these observations, the authors propose PaCRAM, a memory-controller mechanism that partially restores charge and adaptively tunes mitigation thresholds to markedly reduce the overheads of five mainstream RH mitigations, while maintaining data integrity. Evaluations with Ramulator and real-chip insights demonstrate meaningful performance and energy improvements across diverse workloads and configurations, and the work opens the door to scalable, low-cost RowHammer protection. The authors also open-source PaCRAM, enabling immediate use and further research in DRAM reliability and efficiency.

Abstract

RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). To ensure robust DRAM operation, state-of-the-art mitigation mechanisms restore the charge in potential victim rows (i.e., they perform preventive refresh or charge restoration). With newer DRAM chip generations, these mechanisms perform preventive refresh more aggressively and cause larger performance, energy, or area overheads. Therefore, it is essential to develop a better understanding and in-depth insights into the preventive refresh to secure real DRAM chips at low cost. In this paper, our goal is to mitigate RowHammer at low cost by understanding the impact of reduced preventive refresh latency on RowHammer. To this end, we present the first rigorous experimental study on the interactions between refresh latency and RowHammer characteristics in real DRAM chips. Our experimental characterization using 388 real DDR4 DRAM chips from three major manufacturers demonstrates that a preventive refresh latency can be significantly reduced (by 64%). To investigate the impact of reduced preventive refresh latency on system performance and energy efficiency, we reduce the preventive refresh latency and adjust the aggressiveness of existing RowHammer solutions by developing a new mechanism, Partial Charge Restoration for Aggressive Mitigation (PaCRAM). Our results show that PaCRAM reduces the performance and energy overheads induced by five state-of-the-art RowHammer mitigation mechanisms with small additional area overhead. Thus, PaCRAM introduces a novel perspective into addressing RowHammer vulnerability at low cost by leveraging our experimental observations. To aid future research, we open-source our PaCRAM implementation at https://github.com/CMU-SAFARI/PaCRAM.

Figures (19)

• Figure 1: DRAM organization
• Figure 2: Timeline of a DRAM cell's activation process
• Figure 3: Preventive refresh overhead of five RowHammer mitigation mechanisms as RowHammer vulnerability worsens
• Figure 4: Effect of reducing charge restoration latency on the time and energy spent on preventive refreshes
• Figure 5: Photograph of our DRAM Bender infrastructure