PPAC Driven Multi-die and Multi-technology Floorplanning

TL;DR

This work investigates multi-die and multi-technology floorplanning for heterogeneous integration, where blocks can be placed on dies manufactured with different technologies. It introduces MMFP, a framework that jointly optimizes inter-block HPWL, dynamic power, die cost, and timing slack by integrating technology selection with intra- and inter-die placement via simulated annealing and proximal-policy-optimization-based reinforcement learning, underpinned by ML-based PPA estimation and a yield-driven die-cost model. The objective is $f = \omega W + \beta P + \gamma \sum_{d_i} C(d_i) + \tau T$, balancing area, power, cost, and timing across dies. Experimental results on diverse designs and technology pairs show that RL-based MMFP consistently surpasses a naïve baseline, achieving substantial improvements in TNS, power, area, wirelength, and cost, with robust performance gains as the number of dies increases and when hard IPs are present, demonstrating the practical potential for optimized heterogeneous 2.5D/3D IC design.

Abstract

In heterogeneous integration, where different dies may utilize distinct technologies, floorplanning across multiple dies inherently requires simultaneous technology selection. This work presents the first systematic study of multi-die and multi-technology floorplanning. Unlike many conventional approaches, which are primarily driven by area and wirelength, this study additionally considers performance, power, and cost, highlighting the impact of technology selection. A simulated annealing method and a reinforcement learning techniques are developed. Experimental results show that the proposed techniques significantly outperform a naive baseline approach.

Figures (6)

• Figure 1: An overview of the proposed methodology.
• Figure 2: (a) Architecture of fully-connected neural networks for the policy and value function estimation. (b) The B*-tree feature extraction procedure.
• Figure 3: Objective function $f$ value for MMFP-SA/RL across iterations.
• Figure 4: Timing-power tradeoff for MMFP-RL on the vga_lcd design when varying the weighting factors for power ($\beta$) and timing ($\tau$).
• Figure 5: Objective function $f$ value for MMFP-SA/RL that performs inter-die refinement after every $K$ moves/actions.