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Modeling and Simulating Emerging Memory Technologies: A Tutorial

Yun-Chih Chen, Tristan Seidl, Nils Hölscher, Christian Hakert, Minh Duy Truong, Jian-Jia Chen, João Paulo C. de Lima, Asif Ali Khan, Jeronimo Castrillon, Ali Nezhadi, Lokesh Siddhu, Hassan Nassar, Mahta Mayahinia, Mehdi Baradaran Tahoori, Jörg Henkel, Nils Wilbert, Stefan Wildermann, Jürgen Teich

TL;DR

This paper tackles the challenge of evaluating emerging non-volatile memories (NVM) for mainstream computing without access to real devices. It presents a configurable NVM simulation toolchain built on gem5 and NVMain, demonstrated through four case studies: memory-subsystem modeling with DRAM/NVM main memories, wear-out analysis via trace writers, heterogeneous SRAM/STT-RAM caches, and Compute-in-Memory (CiM) architectures. The work details how to configure, extend, and use the toolchain for architecture exploration, including memory timing parameters, cache heterogeneity, and in-memory compute designs, with open-source code and setup instructions to foster reproducibility. The approach enables researchers to study trade-offs in latency, energy, endurance, and data movement before commercial NVMs are widely available, supporting hardware/software co-design and domain-specific optimizations.

Abstract

Non-volatile Memory (NVM) technologies present a promising alternative to traditional volatile memories such as SRAM and DRAM. Due to the limited availability of real NVM devices, simulators play a crucial role in architectural exploration and hardware-software co-design. This tutorial presents a simulation toolchain through four detailed case studies, showcasing its applicability to various domains of system design, including hybrid main-memory and cache, compute-in-memory, and wear-leveling design. These case studies provide the reader with practical insights on customizing the toolchain for their specific research needs. The source code is open-sourced.

Modeling and Simulating Emerging Memory Technologies: A Tutorial

TL;DR

This paper tackles the challenge of evaluating emerging non-volatile memories (NVM) for mainstream computing without access to real devices. It presents a configurable NVM simulation toolchain built on gem5 and NVMain, demonstrated through four case studies: memory-subsystem modeling with DRAM/NVM main memories, wear-out analysis via trace writers, heterogeneous SRAM/STT-RAM caches, and Compute-in-Memory (CiM) architectures. The work details how to configure, extend, and use the toolchain for architecture exploration, including memory timing parameters, cache heterogeneity, and in-memory compute designs, with open-source code and setup instructions to foster reproducibility. The approach enables researchers to study trade-offs in latency, energy, endurance, and data movement before commercial NVMs are widely available, supporting hardware/software co-design and domain-specific optimizations.

Abstract

Non-volatile Memory (NVM) technologies present a promising alternative to traditional volatile memories such as SRAM and DRAM. Due to the limited availability of real NVM devices, simulators play a crucial role in architectural exploration and hardware-software co-design. This tutorial presents a simulation toolchain through four detailed case studies, showcasing its applicability to various domains of system design, including hybrid main-memory and cache, compute-in-memory, and wear-leveling design. These case studies provide the reader with practical insights on customizing the toolchain for their specific research needs. The source code is open-sourced.

Paper Structure

This paper contains 26 sections, 10 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background
  3. NVM Technologies
  4. Commercial Maturity of NVM
  5. NVM Simulation
  6. Studied Toolchains
  7. Case Studies
  8. DRAM and NVMs-Based Main Memory Simulation
  9. Overview
  10. Objective
  11. Methodology
  12. Access Tracing and Data Processing Using Trace Writers
  13. Overview
  14. Objective
  15. Step-By-Step Instructions
  16. ...and 11 more sections

Figures (10)

  • Figure 1: Overview of the NVMain flow. Adapted from poremba:2015khan2019rtsim.
  • Figure 2: Overview of the modifications made to NVMain to support RowClone and its validation
  • Figure 3: Overview of the hybrid volatile/non-volatile memory hierarchies analyzed in this case study.
  • Figure 4: Hybrid (mixed volatile/non-volatile) cache architecture. Visualization on how the nvBlockRatio Parameter influences the technological composition of a cache set.
  • Figure 5: Latency and dynamic energy consumption under different degrees of non-volatility for a write-intensive merge sort application.
  • ...and 5 more figures