DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining

TL;DR

DICE tackles the challenge of pretraining graph representations for device-level ICs that span analog and digital designs. It introduces a simulation-free graph-contrastive pretraining framework that uses two novel augmentations—positive (function-preserving) and negative (function-altering)—to generate diverse, topology-rich training data, and defines a graph-level loss with three relations to learn robust circuit representations. The pretrained DICE encoder is integrated into a three-branch MPNN and evaluated on three graph-level tasks across multiple circuit topologies, showing consistent improvements over baselines and supervised pretraining. This work advances EDA by enabling generalizable, topology-robust device-level representations that reduce labeling and simulation burdens, with potential to accelerate mixed-signal and digital circuit design.

Abstract

Pretraining models with unsupervised graph representation learning has led to significant advancements in domains such as social network analysis, molecular design, and electronic design automation (EDA). However, prior work in EDA has mainly focused on pretraining models for digital circuits, overlooking analog and mixed-signal circuits. To bridge this gap, we introduce DICE, a Device-level Integrated Circuits Encoder, which is the first graph neural network (GNN) pretrained via self-supervised learning specifically tailored for graph-level prediction tasks in both analog and digital circuits. DICE adopts a simulation-free pretraining approach based on graph contrastive learning, leveraging two novel graph augmentation techniques. Experimental results demonstrate substantial performance improvements across three downstream tasks, highlighting the effectiveness of DICE for both analog and digital circuits. The code is available at github.com/brianlsy98/DICE.

Figures (9)

• Figure 1: Key challenges for graph contrastive learning on device-level circuits. (a) Simple graph augmentations, such as randomly adding edges, can break circuit semantics and result in non-equivalent circuits. (b) Existing approaches require training separate models for each circuit topology, limiting the ability to generalize across diverse structures.
• Figure 2: Overview of our graph contrastive learning framework for pretraining DICE. We maximize the cosine similarity between circuits that are in positive relation and minimize it between circuits with a non-equal relation. A detailed explanation of these relations is provided in \ref{['sec:loss']}.
• Figure 3: Rules (a) and examples (b) for positive and negative data augmentation. Positive augmentation adds an identical device in parallel or series, preserving the overall circuit function. Negative augmentation replaces a subgraph, resulting in a circuit with different overall functionality.
• Figure 4: Encoder (a)–Decoder (b) model architecture used for solving downstream tasks. For Parallel GNN 2 and Series GNN, both node and edge features are updated according to Eqs. \ref{['eq:gnn0']}–\ref{['eq:gnn2']}.
• Figure 5: t-SNE visualization of graph-level features. Each plot represents: (a) initial embeddings, embeddings processed by an (b) untrained GNN, (c) GNN pretrained with $\mathcal{L}_{\text{SimSiam}}$, (d) GNN pretrained with $\mathcal{L}_{\text{NT-Xent}}$, and (e) GNN pretrained with $\mathcal{L}_{\text{DICE}}$ (DICE).