A nested MLMC framework for efficient simulations on FPGAs

TL;DR

A new framework is proposed that exploits approximate random variables and fixed-point operations with optimised precision to generate most SDE paths with a lower cost and reduce the overall cost of the MLMC framework.

Abstract

Multilevel Monte Carlo (MLMC) reduces the total computational cost of financial option pricing by combining SDE approximations with multiple resolutions. This paper explores a further avenue for reducing cost and improving power efficiency through the use of low precision calculations on configurable hardware devices such as Field-Programmable Gate Arrays (FPGAs). We propose a new framework that exploits approximate random variables and fixed-point operations with optimised precision to generate most SDE paths with a lower cost and reduce the overall cost of the MLMC framework. We first discuss several methods for the cheap generation of approximate random Normal increments. To set the bit-width of variables in the path generation we then propose a rounding error model and optimise the precision of all variables on each MLMC level. With these key improvements, our proposed framework offers higher computational savings than the existing mixed-precision MLMC frameworks.

Figures (7)

• Figure 1: Mean-squared error for RNG methods 1, 2 (before and after LUT optimisation) and 3 over the bit-width $d$ of the random integer $j$.
• Figure 2: Simulated variance of the error and variance estimates that assume independence or perfect correlation of errors, for $N = 1$ (left) and $N=16$ (right) time steps.
• Figure 3: $\sqrt{\Tilde{C}/C}+ \sqrt{\Tilde{V}/V}$ versus $\lambda$ for levels 0 and 8.
• Figure 4: Optimal bit-widths for each variable, best uniform bit-width, and required RNG accuracy, all versus level.
• Figure 5: $\sqrt{\Tilde{C}/C}+ \sqrt{\Tilde{V}/V}$ versus level for optimal bit-widths and best uniform bit-width.