Fat-Tree QRAM: A High-Bandwidth Shared Quantum Random Access Memory for Parallel Queries

TL;DR

The paper addresses the need for high-bandwidth shared QRAM to support parallel quantum queries. It introduces Fat-Tree QRAM, a multiplexed router architecture that pipelines $O(\log N)$ queries in $O(\log N)$ time using $O(N)$ qubits. It provides both modular and on-chip superconducting implementations, a detailed query-pipelining protocol, and a FIFO-based scheduling algorithm, along with hardware-utilization and error-mitigation analyses. The results show a constant QRAM bandwidth independent of memory size and substantial circuit-depth reductions for parallel algorithms, while maintaining error resilience comparable to BB QRAM and enabling practical fault-tolerance pathways. These findings suggest Fat-Tree QRAM as a viable, scalable shared memory solution for multi-QPU quantum computing.

Abstract

Quantum Random Access Memory (QRAM) is a crucial architectural component for querying classical or quantum data in superposition, enabling algorithms with wide-ranging applications in quantum arithmetic, quantum chemistry, machine learning, and quantum cryptography. In this work, we introduce Fat-Tree QRAM, a novel query architecture capable of pipelining multiple quantum queries simultaneously while maintaining desirable scalings in query speed and fidelity. Specifically, Fat-Tree QRAM performs $O(\log (N))$ independent queries in $O(\log (N))$ time using $O(N)$ qubits, offering immense parallelism benefits over traditional QRAM architectures. To demonstrate its experimental feasibility, we propose modular and on-chip implementations of Fat-Tree QRAM based on superconducting circuits and analyze their performance and fidelity under realistic parameters. Furthermore, a query scheduling protocol is presented to maximize hardware utilization and access the underlying data at an optimal rate. These results suggest that Fat-Tree QRAM is an attractive architecture in a shared memory system for practical quantum computing.

Figures (13)

• Figure 1: (a) Architectural schematics of a shared QRAM that is concurrently accessed by multiple QPUs. (b) Cost comparison between Fat-Tree and Bucket-Brigade (BB) QRAMs for executing $O(\log(N))$ independent queries. The proposed Fat-Tree QRAM allows $O(\log(N))$ queries to be executed in parallel while maintaining desirable asymptotic scalings, including $O(N)$ qubit count, $O(\log(N))$ total latency (i.e., circuit depth), and $O(\log^2(N) \varepsilon)$ infidelity.
• Figure 2: (a) Querying a Bucket-Brigade (BB) QRAM with capacity $N=8$ takes 25 circuit layers. A detailed step-by-step procedure can be found in Appendix \ref{['subsec:BBdetail']}. The circuit layer number indicates the finishing time of each stage. (b) Each quantum router in the BB QRAM involves CSWAP operations between the router qubit and the data qubits. (c) H-tree layout of a BB QRAM. Quantum routers are organized in a binary tree structure, where classical data are located at the leaves. Dashed lines indicate external address and bus qubits that are used to query the QRAM. Figure (c) represents the QRAM state after all address qubits have been loaded, corresponding to circuit layer 15 in (a).
• Figure 3: Layout of a Fat-Tree QRAM with capacity $N=32$ (Similar H-tree layout for BB QRAM appeared in xu2023systems). Classical data are located at the leaves and the internal nodes contain multiplexed quantum routers. Colors of the routers and wires are used to indicate connection. The size of an internal node (i.e., number of qubits) increases linearly as we go up the tree.
• Figure 4: Internal structure of a Fat-Tree node. (a) An example node $(i=1,j=0)$ in a capacity-32 Fat-Tree QRAM, containing 4 routers, 4 incoming wires from the top, and two sets of 3 outgoing wires to its left and right children. (b) A tunable coupler to coaxial wire for inter-node connections in modular design (Sec. \ref{['subsubsec:modular']}). (c) The internal structure of a multiplexed router based on superconducting cavities. Transmon-attached input qubit and router qubit ensure native (cavity-controlled) CSWAP gate implementation weiss2024quantum. Beam splitters between routers provide intra-node connectivity for local swapping operations. (Sec. \ref{['subsec:operation']}) Inset (c1) is an alternative implementation of the router unit enclosed in dashed box that uses more cavities to reduce the connectivity requirement. (d) On-chip two-layer architecture for Fat-Tree QRAM. (Sec. \ref{['subsubsec:onchip']}) (e) Sectional view of on-chip design in (d). Inter-plane connection is achieved by the Through-Substrate-Vias (TSVs) technology.
• Figure 5: An alternative conceptual interpretation of Fat-Tree QRAM as a composition of multiple BB QRAMs of variable size (Sec. \ref{['subsec:operation']}).