Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory

TL;DR

This work tackles CIM noise in RRAM-based neural accelerators by building a cross-layer noise model that merges ADC non-linearity, inter-ADC variation, and RRAM resistance shifts, validated with a 40 nm test-chip. It introduces a method to generate ADC configurations, derive effective bits $b_{eff}$, and inject noise to reflect non-idealities, enabling module-wise and per-ADC reference tuning analyses. The study demonstrates that read disturb can be mitigated with low-voltage read modes and shows that time-dependent tasks (reinforcement learning) are more sensitive to CIM noise than time-independent supervised tasks, with per-ADC tuning providing robust accuracy in challenging cases. Overall, the results offer practical guidance for reliable, energy-efficient CIM hardware across diverse AI workloads by tuning reference voltages at appropriate granularity.

Abstract

With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the nature of analog computation, susceptibility to noise remains a critical concern. This study confronts this challenge by introducing a detailed model that incorporates noise factors arising from both ADCs and RRAM devices. The experimental data is derived from a 40nm foundry RRAM test-chip, wherein different reference voltage configurations are applied, each tailored to its respective module. The mean and standard deviation values of HRS and LRS cells are derived through a randomized vector, forming the foundation for noise simulation within our analytical framework. Additionally, the study examines the read-disturb effects, shedding light on the potential for accuracy deterioration in neural networks due to extended exposure to high-voltage stress. This phenomenon is mitigated through the proposed low-voltage read mode. Leveraging our derived comprehensive fault model from the RRAM test-chip, we evaluate CIM noise impact on both supervised learning (time-independent) and reinforcement learning (time-dependent) tasks, and demonstrate the effectiveness of reference tuning to mitigate noise impacts.

Figures (9)

• Figure 1: Impact of noises on different scenarios, including supervised learning (time-independent) and unsupervised learning (time-dependent). While some adapted effectively to per-module reference adjustments, others necessitated a more refined per-ADC tuning.
• Figure 2: (a) The RRAM macro topology and (b) its symbolic read circuit schematic. Figure adapted from RRAM_CiM_original.
• Figure 3: Mapping voltage states to actual value, where x-axis is golden value and y-axis is voltage states. Red boxes indicate that the voltage state is assigned to that specific target code.
• Figure 4: The histogram of the correct output, under a CIM array (9 $\times$ 64 accumulate groups, spams across 8 ADCs) of 50% HRS and 50% LRS. The input consists of 256 different combinations among 9 WLs.
• Figure 5: Measuring the effective bits of (a) actual v.s. golden response and (b) actual v.s. fitted response, under 512 WL combinations.