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Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate

Yifei Jin, Dimitrios Koutlis, Hector Bandala, Marios Daoutis

TL;DR

This paper tackles the computational burden of IR drop estimation in modern ASICs by introducing Graph Neural Networks (GNNs) as fast, accurate surrogates. It develops a graph-based representation where edges encode net proximity via Manhattan distance and compares GCN, GIN, and GAT architectures against XGBoost and CNN baselines, using two feature sets (A and B) that incorporate timing data. The results show that GIN (and GCN variants) can achieve lower prediction errors and significantly faster runtimes than commercial tools, with Set B timing features yielding the strongest performance and safety margins well within supply limits. Overall, the study demonstrates the potential of GNNs to accelerate IR drop prediction and improve power integrity planning in ASIC sign-off, with implications for energy efficiency and environmental impact.

Abstract

Accurate estimation of voltage drop (IR drop) in modern Application-Specific Integrated Circuits (ASICs) is highly time and resource demanding, due to the growing complexity and the transistor density in recent technology nodes. To mitigate this challenge, we investigate how Machine Learning (ML) techniques, including Extreme Gradient Boosting (XGBoost), Convolutional Neural Network (CNN), and Graph Neural Network (GNN) can aid in reducing the computational effort and implicitly the time required to estimate the IR drop in Integrated Circuits (ICs). Traditional methods, including commercial tools, require considerable time to produce accurate approximations, especially for complicated designs with numerous transistors. ML algorithms, on the other hand, are explored as an alternative solution to offer quick and precise IR drop estimation, but in considerably less time. Our approach leverages ASICs' electrical, timing, and physical to train ML models, ensuring adaptability across diverse designs with minimal adjustments. Experimental results underscore the superiority of ML models over commercial tools, greatly enhancing prediction speed. Particularly, GNNs exhibit promising performance with minimal prediction errors in voltage drop estimation. The incorporation of GNNs marks a groundbreaking advancement in accurate IR drop prediction. This study illustrates the effectiveness of ML algorithms in precisely estimating IR drop and optimizing ASIC sign-off. Utilizing ML models leads to expedited predictions, reducing calculation time and improving energy efficiency, thereby reducing environmental impact through optimized power circuits.

Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate

TL;DR

This paper tackles the computational burden of IR drop estimation in modern ASICs by introducing Graph Neural Networks (GNNs) as fast, accurate surrogates. It develops a graph-based representation where edges encode net proximity via Manhattan distance and compares GCN, GIN, and GAT architectures against XGBoost and CNN baselines, using two feature sets (A and B) that incorporate timing data. The results show that GIN (and GCN variants) can achieve lower prediction errors and significantly faster runtimes than commercial tools, with Set B timing features yielding the strongest performance and safety margins well within supply limits. Overall, the study demonstrates the potential of GNNs to accelerate IR drop prediction and improve power integrity planning in ASIC sign-off, with implications for energy efficiency and environmental impact.

Abstract

Accurate estimation of voltage drop (IR drop) in modern Application-Specific Integrated Circuits (ASICs) is highly time and resource demanding, due to the growing complexity and the transistor density in recent technology nodes. To mitigate this challenge, we investigate how Machine Learning (ML) techniques, including Extreme Gradient Boosting (XGBoost), Convolutional Neural Network (CNN), and Graph Neural Network (GNN) can aid in reducing the computational effort and implicitly the time required to estimate the IR drop in Integrated Circuits (ICs). Traditional methods, including commercial tools, require considerable time to produce accurate approximations, especially for complicated designs with numerous transistors. ML algorithms, on the other hand, are explored as an alternative solution to offer quick and precise IR drop estimation, but in considerably less time. Our approach leverages ASICs' electrical, timing, and physical to train ML models, ensuring adaptability across diverse designs with minimal adjustments. Experimental results underscore the superiority of ML models over commercial tools, greatly enhancing prediction speed. Particularly, GNNs exhibit promising performance with minimal prediction errors in voltage drop estimation. The incorporation of GNNs marks a groundbreaking advancement in accurate IR drop prediction. This study illustrates the effectiveness of ML algorithms in precisely estimating IR drop and optimizing ASIC sign-off. Utilizing ML models leads to expedited predictions, reducing calculation time and improving energy efficiency, thereby reducing environmental impact through optimized power circuits.

Paper Structure

This paper contains 13 sections, 1 equation, 13 figures, 3 tables, 1 algorithm.

Figures (13)

  • Figure 1: Representation of voltage drop and ground bounce waveform
  • Figure 2: Typical IR drop analysis steps
  • Figure 3: ML model and CNN architecture of PowerNet Xie_powernet
  • Figure 4: ASIC test circuit
  • Figure 5: Layout of test circuit
  • ...and 8 more figures